Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	53702190	107026	0	0
StatusRise_A	53702190	120521	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53702190	107026	0	0
T2	8334	54	0	0
T3	909621	1274	0	0
T4	254808	353	0	0
T5	2520	9	0	0
T6	5226	0	0	0
T7	14160	54	0	0
T8	32631	50	0	0
T9	6612	0	0	0
T10	182673	204	0	0
T37	11883	8	0	0
T38	0	59	0	0
T69	0	41	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53702190	120521	0	0
T1	5916	6	0	0
T2	8334	60	0	0
T3	909621	1444	0	0
T4	254808	408	0	0
T5	2520	12	0	0
T6	5226	18	0	0
T7	14160	57	0	0
T8	32631	67	0	0
T9	6612	15	0	0
T10	182673	207	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17900730	39682	0	0
StatusRise_A	17900730	44507	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	39682	0	0
T2	2778	18	0	0
T3	303207	462	0	0
T4	84936	132	0	0
T5	840	3	0	0
T6	1742	0	0	0
T7	4720	18	0	0
T8	10877	20	0	0
T9	2204	0	0	0
T10	60891	83	0	0
T37	3961	3	0	0
T38	0	20	0	0
T69	0	15	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	44507	0	0
T1	1972	2	0	0
T2	2778	20	0	0
T3	303207	524	0	0
T4	84936	151	0	0
T5	840	4	0	0
T6	1742	6	0	0
T7	4720	19	0	0
T8	10877	26	0	0
T9	2204	5	0	0
T10	60891	84	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17900730	39682	0	0
StatusRise_A	17900730	44507	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	39682	0	0
T2	2778	18	0	0
T3	303207	462	0	0
T4	84936	132	0	0
T5	840	3	0	0
T6	1742	0	0	0
T7	4720	18	0	0
T8	10877	20	0	0
T9	2204	0	0	0
T10	60891	83	0	0
T37	3961	3	0	0
T38	0	20	0	0
T69	0	15	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	44507	0	0
T1	1972	2	0	0
T2	2778	20	0	0
T3	303207	524	0	0
T4	84936	151	0	0
T5	840	4	0	0
T6	1742	6	0	0
T7	4720	19	0	0
T8	10877	26	0	0
T9	2204	5	0	0
T10	60891	84	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17900730	27662	0	0
StatusRise_A	17900730	31507	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	27662	0	0
T2	2778	18	0	0
T3	303207	350	0	0
T4	84936	89	0	0
T5	840	3	0	0
T6	1742	0	0	0
T7	4720	18	0	0
T8	10877	10	0	0
T9	2204	0	0	0
T10	60891	38	0	0
T37	3961	2	0	0
T38	0	19	0	0
T69	0	11	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	31507	0	0
T1	1972	2	0	0
T2	2778	20	0	0
T3	303207	396	0	0
T4	84936	106	0	0
T5	840	4	0	0
T6	1742	6	0	0
T7	4720	19	0	0
T8	10877	15	0	0
T9	2204	5	0	0
T10	60891	39	0	0