Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	17901357	9799	0	0
EscTimeoutStoppedByClReset_A	17900730	2459341	0	0
EscTimeoutTriggersReset_A	3864781	465	0	0
RomAllowActiveState_A	17900730	44084	0	0
RomAllowCheckGoodState_A	17900730	44135	0	0
RomBlockActiveState_A	17900730	26920	0	0
RomBlockCheckGoodState_A	17900730	394911	0	0
RomIntgChkDisFalse_A	17900730	17360003	0	0
RomIntgChkDisTrue_A	17900730	117229	0	0
RstreqChkEsctimeout_A	17900730	3392	0	0
RstreqChkFsmterm_A	17900730	180	0	0
RstreqChkGlbesc_A	17900730	3392	0	0
RstreqChkMainpd_A	17900730	774592	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17901357	9799	0	0
T11	9505	38	0	0
T12	0	23	0	0
T13	0	107	0	0
T19	210383	0	0	0
T22	51848	0	0	0
T39	3809	0	0	0
T41	1962	0	0	0
T46	21776	0	0	0
T80	54096	0	0	0
T81	2687	0	0	0
T82	2288	0	0	0
T125	5628	0	0	0
T129	0	8	0	0
T130	0	203	0	0
T131	0	62	0	0
T132	0	9	0	0
T133	0	18	0	0
T134	0	88	0	0
T135	0	363	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	2459341	0	0
T1	1972	31	0	0
T2	2778	330	0	0
T3	303207	40478	0	0
T4	84936	13619	0	0
T5	840	0	0	0
T6	1742	16	0	0
T7	4720	331	0	0
T8	10877	1196	0	0
T9	2204	22	0	0
T10	60891	13260	0	0
T37	0	796	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3864781	465	0	0
T11	701	4	0	0
T12	0	3	0	0
T13	0	4	0	0
T19	160989	0	0	0
T22	5023	0	0	0
T39	335	0	0	0
T41	170	0	0	0
T46	8595	0	0	0
T80	5701	0	0	0
T81	964	0	0	0
T82	202	0	0	0
T125	672	0	0	0
T129	0	8	0	0
T130	0	5	0	0
T131	0	4	0	0
T132	0	5	0	0
T133	0	4	0	0
T134	0	5	0	0
T136	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	44084	0	0
T1	1972	2	0	0
T2	2778	13	0	0
T3	303207	521	0	0
T4	84936	151	0	0
T5	840	4	0	0
T6	1742	6	0	0
T7	4720	12	0	0
T8	10877	26	0	0
T9	2204	5	0	0
T10	60891	84	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	44135	0	0
T1	1972	2	0	0
T2	2778	14	0	0
T3	303207	521	0	0
T4	84936	151	0	0
T5	840	4	0	0
T6	1742	6	0	0
T7	4720	13	0	0
T8	10877	26	0	0
T9	2204	5	0	0
T10	60891	84	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	26920	0	0
T11	9504	0	0	0
T19	210382	0	0	0
T21	20373	5	0	0
T22	51848	0	0	0
T39	3808	0	0	0
T41	1962	0	0	0
T46	21775	2	0	0
T47	0	25	0	0
T71	2851	0	0	0
T80	54095	0	0	0
T81	2686	0	0	0
T137	0	548	0	0
T138	0	297	0	0
T139	0	297	0	0
T140	0	358	0	0
T141	0	661	0	0
T142	0	1488	0	0
T143	0	307	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	394911	0	0
T3	303207	1304	0	0
T4	84936	458	0	0
T5	840	0	0	0
T6	1742	0	0	0
T7	4720	0	0	0
T8	10877	276	0	0
T9	2204	0	0	0
T10	60891	3933	0	0
T20	0	4029	0	0
T21	0	1282	0	0
T22	0	4073	0	0
T33	0	367	0	0
T35	0	4139	0	0
T37	3961	0	0	0
T38	2614	0	0	0
T80	0	4127	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	17360003	0	0
T1	1972	1830	0	0
T2	2778	1811	0	0
T3	303207	298599	0	0
T4	84936	83565	0	0
T5	840	750	0	0
T6	1742	1265	0	0
T7	4720	3827	0	0
T8	10877	10430	0	0
T9	2204	1817	0	0
T10	60891	60836	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	117229	0	0
T11	9504	0	0	0
T20	57745	1169	0	0
T21	20373	494	0	0
T22	51848	895	0	0
T41	1962	0	0	0
T42	3412	0	0	0
T44	2642	0	0	0
T46	0	526	0	0
T47	0	277	0	0
T71	2851	0	0	0
T80	54095	199	0	0
T81	2686	0	0	0
T137	0	340	0	0
T138	0	1351	0	0
T139	0	104	0	0
T144	0	15648	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	3392	0	0
T1	1972	1	0	0
T2	2778	6	0	0
T3	303207	37	0	0
T4	84936	19	0	0
T5	840	0	0	0
T6	1742	0	0	0
T7	4720	4	0	0
T8	10877	0	0	0
T9	2204	4	0	0
T10	60891	0	0	0
T11	0	2	0	0
T34	0	9	0	0
T36	0	5	0	0
T41	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	180	0	0
T16	43624	40	0	0
T17	9501	20	0	0
T18	0	40	0	0
T23	0	40	0	0
T24	0	40	0	0
T25	39377	0	0	0
T26	3184	0	0	0
T27	16755	0	0	0
T28	215147	0	0	0
T29	10525	0	0	0
T30	22685	0	0	0
T31	3265	0	0	0
T32	2189	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	3392	0	0
T1	1972	1	0	0
T2	2778	6	0	0
T3	303207	37	0	0
T4	84936	19	0	0
T5	840	0	0	0
T6	1742	0	0	0
T7	4720	4	0	0
T8	10877	0	0	0
T9	2204	4	0	0
T10	60891	0	0	0
T11	0	2	0	0
T34	0	9	0	0
T36	0	5	0	0
T41	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17900730	774592	0	0
T2	2778	103	0	0
T3	303207	7091	0	0
T4	84936	2797	0	0
T5	840	0	0	0
T6	1742	28	0	0
T7	4720	117	0	0
T8	10877	507	0	0
T9	2204	0	0	0
T10	60891	4129	0	0
T33	0	333	0	0
T34	0	308	0	0
T35	0	6114	0	0
T37	3961	0	0	0