Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	351492	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

139459

1

T1

31

T2

5

T3

183

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	256110	1			T1	65		T2	6		T3	411
values[0x0]	117290	1			T1	30		T2	11		T3	205
values[0x1]	117551	1			T1	34		T2	5		T3	247

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	278001	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

212950

1

T1

44

T2

7

T3

330

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1401	1			T3	1		T4	1		T8	1
valid_sources[0x01]	1379	1			T3	4		T8	3		T23	1
valid_sources[0x02]	1659	1			T1	1		T3	3		T8	1
valid_sources[0x03]	1993	1			T3	3		T7	2		T23	4
valid_sources[0x04]	2029	1			T1	1		T3	2		T23	3
valid_sources[0x05]	1405	1			T1	1		T4	3		T6	5
valid_sources[0x06]	5163	1			T3	5		T4	1		T7	13
valid_sources[0x07]	1520	1			T3	3		T4	2		T6	4
valid_sources[0x08]	1700	1			T1	1		T3	6		T4	1
valid_sources[0x09]	1715	1			T3	1		T23	4		T14	46
valid_sources[0x0a]	1481	1			T1	1		T3	2		T8	2
valid_sources[0x0b]	3199	1			T1	1		T4	4		T37	1
valid_sources[0x0c]	1543	1			T1	1		T3	2		T4	1
valid_sources[0x0d]	1602	1			T4	5		T7	2		T8	1
valid_sources[0x0e]	1503	1			T8	1		T21	3		T35	3
valid_sources[0x0f]	2111	1			T3	2		T37	2		T23	1
valid_sources[0x10]	2638	1			T1	1		T3	2		T7	5
valid_sources[0x11]	2283	1			T3	2		T7	3		T8	1
valid_sources[0x12]	1660	1			T1	1		T3	5		T4	1
valid_sources[0x13]	3816	1			T1	1		T3	10		T23	4
valid_sources[0x14]	1470	1			T1	3		T3	4		T10	1
valid_sources[0x15]	1614	1			T3	5		T7	5		T10	3
valid_sources[0x16]	1787	1			T3	4		T6	2		T23	3
valid_sources[0x17]	2179	1			T3	3		T7	13		T23	1
valid_sources[0x18]	1488	1			T3	4		T7	14		T8	2
valid_sources[0x19]	1747	1			T1	1		T4	1		T23	2
valid_sources[0x1a]	1553	1			T1	1		T3	7		T8	2
valid_sources[0x1b]	1486	1			T3	2		T4	1		T8	1
valid_sources[0x1c]	1393	1			T1	2		T3	1		T6	4
valid_sources[0x1d]	2996	1			T1	1		T3	3		T4	2
valid_sources[0x1e]	3206	1			T1	1		T3	4		T7	19
valid_sources[0x1f]	2203	1			T3	6		T4	2		T6	2
valid_sources[0x20]	1840	1			T1	1		T3	8		T4	1
valid_sources[0x21]	3383	1			T3	3		T4	2		T6	1
valid_sources[0x22]	1354	1			T3	3		T4	1		T7	2
valid_sources[0x23]	1468	1			T3	1		T4	3		T23	7
valid_sources[0x24]	4524	1			T1	1		T3	2		T4	2
valid_sources[0x25]	1680	1			T3	2		T4	3		T8	1
valid_sources[0x26]	1476	1			T3	5		T4	1		T37	1
valid_sources[0x27]	1446	1			T3	3		T4	1		T6	2
valid_sources[0x28]	1815	1			T1	1		T8	1		T23	2
valid_sources[0x29]	2229	1			T3	3		T4	1		T6	9
valid_sources[0x2a]	3211	1			T3	3		T4	3		T7	5
valid_sources[0x2b]	1521	1			T3	3		T4	1		T7	12
valid_sources[0x2c]	1428	1			T1	1		T3	2		T4	2
valid_sources[0x2d]	1543	1			T1	1		T3	3		T8	1
valid_sources[0x2e]	1501	1			T3	2		T8	3		T37	1
valid_sources[0x2f]	2813	1			T1	1		T3	4		T4	1
valid_sources[0x30]	2588	1			T1	2		T3	2		T4	6
valid_sources[0x31]	1606	1			T14	47		T21	11		T22	28
valid_sources[0x32]	1563	1			T3	1		T4	1		T23	2
valid_sources[0x33]	3089	1			T3	2		T4	1		T6	2
valid_sources[0x34]	1663	1			T3	1		T4	1		T8	2
valid_sources[0x35]	1520	1			T3	1		T4	2		T8	1
valid_sources[0x36]	1636	1			T3	2		T8	1		T10	4
valid_sources[0x37]	1950	1			T3	3		T4	1		T7	2
valid_sources[0x38]	3545	1			T8	1		T14	16		T21	4
valid_sources[0x39]	1540	1			T1	1		T4	1		T8	1
valid_sources[0x3a]	1510	1			T3	3		T4	3		T23	5
valid_sources[0x3b]	1350	1			T1	1		T3	3		T8	2
valid_sources[0x3c]	2465	1			T3	2		T7	2		T8	2
valid_sources[0x3d]	1524	1			T3	5		T7	2		T23	1
valid_sources[0x3e]	1568	1			T1	2		T3	5		T4	1
valid_sources[0x3f]	1896	1			T3	2		T7	1		T10	1
valid_sources[0x40]	1884	1			T3	7		T10	2		T23	6
valid_sources[0x41]	1549	1			T1	1		T3	4		T4	2
valid_sources[0x42]	1457	1			T1	1		T3	8		T4	1
valid_sources[0x43]	1411	1			T3	7		T4	1		T5	1
valid_sources[0x44]	1379	1			T3	1		T6	7		T37	1
valid_sources[0x45]	2419	1			T1	1		T3	9		T4	2
valid_sources[0x46]	1414	1			T3	3		T4	1		T6	7
valid_sources[0x47]	1578	1			T3	2		T4	1		T23	2
valid_sources[0x48]	1651	1			T3	8		T4	1		T8	1
valid_sources[0x49]	1602	1			T3	1		T23	2		T14	36
valid_sources[0x4a]	2444	1			T1	2		T3	3		T7	5
valid_sources[0x4b]	1444	1			T1	1		T3	3		T4	6
valid_sources[0x4c]	1570	1			T3	8		T4	1		T23	3
valid_sources[0x4d]	1522	1			T1	1		T3	4		T4	2
valid_sources[0x4e]	1603	1			T1	3		T3	2		T23	12
valid_sources[0x4f]	1612	1			T1	1		T3	4		T8	1
valid_sources[0x50]	1620	1			T3	2		T4	1		T37	1
valid_sources[0x51]	2512	1			T3	3		T8	2		T23	6
valid_sources[0x52]	4070	1			T3	1		T4	2		T6	3
valid_sources[0x53]	1432	1			T3	3		T10	3		T23	5
valid_sources[0x54]	1755	1			T3	6		T4	1		T8	4
valid_sources[0x55]	1306	1			T3	1		T37	1		T23	3
valid_sources[0x56]	2518	1			T3	2		T23	4		T14	1
valid_sources[0x57]	1588	1			T3	8		T4	1		T23	3
valid_sources[0x58]	2326	1			T3	5		T4	1		T7	31
valid_sources[0x59]	1435	1			T4	2		T23	8		T21	4
valid_sources[0x5a]	3107	1			T1	1		T3	5		T4	1
valid_sources[0x5b]	1409	1			T1	1		T3	5		T4	5
valid_sources[0x5c]	1577	1			T4	2		T10	3		T37	2
valid_sources[0x5d]	1512	1			T1	1		T3	1		T4	1
valid_sources[0x5e]	1491	1			T3	2		T7	39		T23	2
valid_sources[0x5f]	1426	1			T1	1		T3	1		T23	4
valid_sources[0x60]	1347	1			T3	3		T4	5		T23	1
valid_sources[0x61]	1473	1			T1	1		T3	4		T4	1
valid_sources[0x62]	1535	1			T1	1		T4	5		T7	16
valid_sources[0x63]	1726	1			T3	3		T4	4		T7	1
valid_sources[0x64]	4865	1			T3	2		T6	1		T23	3
valid_sources[0x65]	2248	1			T3	3		T7	32		T10	2
valid_sources[0x66]	1437	1			T3	4		T6	3		T23	1
valid_sources[0x67]	2456	1			T3	3		T4	3		T7	1
valid_sources[0x68]	1987	1			T1	2		T3	3		T23	3
valid_sources[0x69]	1686	1			T3	3		T10	1		T23	1
valid_sources[0x6a]	1628	1			T1	1		T3	3		T8	1
valid_sources[0x6b]	1591	1			T1	1		T3	9		T4	3
valid_sources[0x6c]	1428	1			T3	5		T23	2		T21	7
valid_sources[0x6d]	1749	1			T3	5		T4	1		T6	11
valid_sources[0x6e]	3477	1			T3	3		T6	3		T10	1
valid_sources[0x6f]	1263	1			T3	4		T4	1		T23	5
valid_sources[0x70]	1420	1			T1	2		T3	5		T4	1
valid_sources[0x71]	1643	1			T3	4		T4	3		T8	1
valid_sources[0x72]	1439	1			T3	3		T4	3		T8	3
valid_sources[0x73]	1571	1			T3	8		T4	2		T7	1
valid_sources[0x74]	1472	1			T3	11		T4	2		T23	12
valid_sources[0x75]	1899	1			T3	4		T7	6		T23	5
valid_sources[0x76]	2306	1			T3	3		T10	1		T23	3
valid_sources[0x77]	1459	1			T1	1		T3	7		T4	2
valid_sources[0x78]	3078	1			T1	1		T3	6		T4	2
valid_sources[0x79]	2070	1			T23	4		T14	21		T22	31
valid_sources[0x7a]	2153	1			T4	1		T8	1		T23	9
valid_sources[0x7b]	1464	1			T3	3		T4	1		T8	4
valid_sources[0x7c]	1514	1			T1	1		T3	6		T7	17
valid_sources[0x7d]	1610	1			T1	1		T3	9		T4	1
valid_sources[0x7e]	1347	1			T1	1		T4	2		T23	3
valid_sources[0x7f]	1851	1			T1	2		T3	4		T4	1
valid_sources[0x80]	1567	1			T1	2		T3	1		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

69205

1

T1

16

T2

2

T3

73

values[0x0]

all_enables

biggest_size

45041

1

T1

10

T2

3

T3

77

values[0x1]

all_enables

biggest_size

25213

1

T1

5

T3

33

T4

3