SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34950 | 1 | T3 | 414 | T23 | 296 | T14 | 1 | ||||
others[1] | 34952 | 1 | T3 | 371 | T23 | 316 | T24 | 295 | ||||
others[2] | 35075 | 1 | T3 | 366 | T23 | 305 | T24 | 297 | ||||
others[3] | 58482 | 1 | T3 | 708 | T23 | 486 | T14 | 1 | ||||
false | 13954 | 1 | T3 | 50 | T23 | 50 | T14 | 189 | ||||
true | 22291 | 1 | T1 | 1 | T2 | 5 | T3 | 102 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34827 | 1 | T3 | 395 | T23 | 302 | T14 | 1 | ||||
others[1] | 35052 | 1 | T3 | 407 | T23 | 288 | T24 | 314 | ||||
others[2] | 35157 | 1 | T3 | 397 | T23 | 303 | T14 | 1 | ||||
others[3] | 58708 | 1 | T3 | 668 | T23 | 514 | T24 | 481 | ||||
false | 9564 | 1 | T3 | 50 | T23 | 50 | T14 | 96 | ||||
true | 17958 | 1 | T1 | 1 | T2 | 5 | T3 | 102 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 536 | 1 | T9 | 1 | T14 | 3 | T36 | 1 | ||||
others[1] | 581 | 1 | T14 | 3 | T35 | 1 | T25 | 1 | ||||
others[2] | 538 | 1 | T4 | 1 | T9 | 1 | T14 | 2 | ||||
others[3] | 890 | 1 | T4 | 2 | T9 | 1 | T14 | 6 | ||||
false | 9959 | 1 | T1 | 1 | T2 | 5 | T3 | 2 | ||||
true | 2722 | 1 | T4 | 6 | T9 | 8 | T14 | 34 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |