Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T14

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	15906564	4774	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	15906564	196998	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	15906564	6350510	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	15906564	196966	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	15906564	4774	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	15906564	196998	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	15906564	6350510	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	15906564	196966	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	4774	0	0
T2	2170	1	0	0
T3	18007	17	0	0
T4	7089	0	0	0
T5	1265	0	0	0
T6	14779	0	0	0
T7	3272	0	0	0
T8	2681	0	0	0
T9	2318	0	0	0
T10	4435	0	0	0
T14	0	55	0	0
T21	0	13	0	0
T22	0	62	0	0
T23	0	21	0	0
T24	0	17	0	0
T37	2087	1	0	0
T41	0	3	0	0
T72	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	196998	0	0
T2	2170	112	0	0
T3	18007	443	0	0
T4	7089	0	0	0
T5	1265	0	0	0
T6	14779	0	0	0
T7	3272	0	0	0
T8	2681	0	0	0
T9	2318	0	0	0
T10	4435	0	0	0
T14	0	1487	0	0
T21	0	333	0	0
T22	0	3925	0	0
T23	0	1166	0	0
T24	0	693	0	0
T37	2087	9	0	0
T41	0	243	0	0
T72	0	13	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	6350510	0	0
T1	10108	2111	0	0
T2	2170	136	0	0
T3	18007	7213	0	0
T4	7089	0	0	0
T5	1265	0	0	0
T6	14779	6763	0	0
T7	3272	516	0	0
T8	2681	1404	0	0
T9	2318	0	0	0
T10	4435	1579	0	0
T14	0	42402	0	0
T23	0	21001	0	0
T37	0	1328	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	196966	0	0
T2	2170	112	0	0
T3	18007	443	0	0
T4	7089	0	0	0
T5	1265	0	0	0
T6	14779	0	0	0
T7	3272	0	0	0
T8	2681	0	0	0
T9	2318	0	0	0
T10	4435	0	0	0
T14	0	1487	0	0
T21	0	333	0	0
T22	0	3921	0	0
T23	0	1166	0	0
T24	0	693	0	0
T37	2087	9	0	0
T41	0	243	0	0
T72	0	13	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	4774	0	0
T2	2170	1	0	0
T3	18007	17	0	0
T4	7089	0	0	0
T5	1265	0	0	0
T6	14779	0	0	0
T7	3272	0	0	0
T8	2681	0	0	0
T9	2318	0	0	0
T10	4435	0	0	0
T14	0	55	0	0
T21	0	13	0	0
T22	0	62	0	0
T23	0	21	0	0
T24	0	17	0	0
T37	2087	1	0	0
T41	0	3	0	0
T72	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	196998	0	0
T2	2170	112	0	0
T3	18007	443	0	0
T4	7089	0	0	0
T5	1265	0	0	0
T6	14779	0	0	0
T7	3272	0	0	0
T8	2681	0	0	0
T9	2318	0	0	0
T10	4435	0	0	0
T14	0	1487	0	0
T21	0	333	0	0
T22	0	3925	0	0
T23	0	1166	0	0
T24	0	693	0	0
T37	2087	9	0	0
T41	0	243	0	0
T72	0	13	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	6350510	0	0
T1	10108	2111	0	0
T2	2170	136	0	0
T3	18007	7213	0	0
T4	7089	0	0	0
T5	1265	0	0	0
T6	14779	6763	0	0
T7	3272	516	0	0
T8	2681	1404	0	0
T9	2318	0	0	0
T10	4435	1579	0	0
T14	0	42402	0	0
T23	0	21001	0	0
T37	0	1328	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	196966	0	0
T2	2170	112	0	0
T3	18007	443	0	0
T4	7089	0	0	0
T5	1265	0	0	0
T6	14779	0	0	0
T7	3272	0	0	0
T8	2681	0	0	0
T9	2318	0	0	0
T10	4435	0	0	0
T14	0	1487	0	0
T21	0	333	0	0
T22	0	3921	0	0
T23	0	1166	0	0
T24	0	693	0	0
T37	2087	9	0	0
T41	0	243	0	0
T72	0	13	0	0