Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	16525937	17409	0	0
intr_enable_rd_A	16525937	24684	0	0
reset_en_rd_A	16525937	1066	0	0
reset_en_regwen_rd_A	16525937	915	0	0
wake_info_capture_dis_rd_A	16525937	836	0	0
wakeup_en_rd_A	16525937	1851	0	0
wakeup_en_regwen_rd_A	16525937	963	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16525937	17409	0	0
T11	10974	0	0	0
T14	97642	16	0	0
T16	3075	0	0	0
T21	47967	7	0	0
T22	286204	155	0	0
T24	35404	0	0	0
T25	1384	0	0	0
T29	0	14	0	0
T35	3387	0	0	0
T36	3318	0	0	0
T47	0	49	0	0
T51	0	23	0	0
T72	1328	0	0	0
T73	0	6	0	0
T88	0	46	0	0
T126	0	19	0	0
T127	0	44	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16525937	24684	0	0
T1	10108	13	0	0
T2	2170	0	0	0
T3	18007	0	0	0
T4	7089	0	0	0
T5	1265	0	0	0
T6	14779	28	0	0
T7	3272	0	0	0
T8	2681	0	0	0
T9	2318	0	0	0
T10	4435	24	0	0
T21	0	353	0	0
T24	0	137	0	0
T28	0	107	0	0
T29	0	692	0	0
T30	0	15	0	0
T85	0	193	0	0
T128	0	6	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16525937	1066	0	0
T11	10974	0	0	0
T16	3075	0	0	0
T17	1099	0	0	0
T21	47967	6	0	0
T22	286204	0	0	0
T24	35404	0	0	0
T25	1384	0	0	0
T29	0	14	0	0
T35	3387	0	0	0
T36	3318	0	0	0
T49	0	41	0	0
T72	1328	0	0	0
T73	0	10	0	0
T88	0	15	0	0
T129	0	7	0	0
T130	0	9	0	0
T131	0	11	0	0
T132	0	1	0	0
T133	0	17	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16525937	915	0	0
T11	10974	0	0	0
T16	3075	0	0	0
T17	1099	0	0	0
T21	47967	14	0	0
T22	286204	0	0	0
T24	35404	0	0	0
T25	1384	0	0	0
T29	0	1	0	0
T35	3387	0	0	0
T36	3318	0	0	0
T49	0	64	0	0
T72	1328	0	0	0
T73	0	14	0	0
T76	0	3	0	0
T88	0	21	0	0
T129	0	13	0	0
T131	0	3	0	0
T132	0	6	0	0
T133	0	21	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16525937	836	0	0
T11	10974	0	0	0
T16	3075	0	0	0
T17	1099	0	0	0
T21	47967	13	0	0
T22	286204	0	0	0
T24	35404	0	0	0
T25	1384	0	0	0
T29	0	16	0	0
T35	3387	0	0	0
T36	3318	0	0	0
T49	0	50	0	0
T72	1328	0	0	0
T73	0	22	0	0
T76	0	9	0	0
T88	0	23	0	0
T129	0	16	0	0
T131	0	6	0	0
T132	0	15	0	0
T133	0	11	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16525937	1851	0	0
T11	10974	0	0	0
T16	3075	0	0	0
T17	1099	0	0	0
T21	47967	14	0	0
T22	286204	0	0	0
T24	35404	0	0	0
T25	1384	0	0	0
T29	0	17	0	0
T35	3387	0	0	0
T36	3318	0	0	0
T72	1328	0	0	0
T73	0	25	0	0
T76	0	10	0	0
T88	0	15	0	0
T129	0	13	0	0
T130	0	2	0	0
T131	0	12	0	0
T132	0	7	0	0
T133	0	10	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16525937	963	0	0
T11	10974	0	0	0
T16	3075	0	0	0
T17	1099	0	0	0
T21	47967	10	0	0
T22	286204	0	0	0
T24	35404	0	0	0
T25	1384	0	0	0
T29	0	10	0	0
T35	3387	0	0	0
T36	3318	0	0	0
T72	1328	0	0	0
T73	0	6	0	0
T76	0	8	0	0
T88	0	19	0	0
T129	0	24	0	0
T130	0	7	0	0
T131	0	6	0	0
T132	0	6	0	0
T133	0	30	0	0