Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	47719692	98842	0	0
StatusRise_A	47719692	111088	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47719692	98842	0	0
T1	30324	23	0	0
T2	6510	12	0	0
T3	54021	208	0	0
T4	21267	54	0	0
T5	3795	0	0	0
T6	44337	38	0	0
T7	9816	54	0	0
T8	8043	38	0	0
T9	6954	42	0	0
T10	13305	17	0	0
T37	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47719692	111088	0	0
T1	30324	26	0	0
T2	6510	15	0	0
T3	54021	214	0	0
T4	21267	57	0	0
T5	3795	9	0	0
T6	44337	40	0	0
T7	9816	56	0	0
T8	8043	40	0	0
T9	6954	45	0	0
T10	13305	20	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	15906564	36839	0	0
StatusRise_A	15906564	41211	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	36839	0	0
T1	10108	9	0	0
T2	2170	4	0	0
T3	18007	82	0	0
T4	7089	18	0	0
T5	1265	0	0	0
T6	14779	14	0	0
T7	3272	20	0	0
T8	2681	14	0	0
T9	2318	14	0	0
T10	4435	6	0	0
T37	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	41211	0	0
T1	10108	10	0	0
T2	2170	5	0	0
T3	18007	84	0	0
T4	7089	19	0	0
T5	1265	3	0	0
T6	14779	15	0	0
T7	3272	21	0	0
T8	2681	15	0	0
T9	2318	15	0	0
T10	4435	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	15906564	36839	0	0
StatusRise_A	15906564	41226	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	36839	0	0
T1	10108	9	0	0
T2	2170	4	0	0
T3	18007	82	0	0
T4	7089	18	0	0
T5	1265	0	0	0
T6	14779	14	0	0
T7	3272	20	0	0
T8	2681	14	0	0
T9	2318	14	0	0
T10	4435	6	0	0
T37	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	41226	0	0
T1	10108	10	0	0
T2	2170	5	0	0
T3	18007	84	0	0
T4	7089	19	0	0
T5	1265	3	0	0
T6	14779	15	0	0
T7	3272	21	0	0
T8	2681	15	0	0
T9	2318	15	0	0
T10	4435	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	15906564	25164	0	0
StatusRise_A	15906564	28651	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	25164	0	0
T1	10108	5	0	0
T2	2170	4	0	0
T3	18007	44	0	0
T4	7089	18	0	0
T5	1265	0	0	0
T6	14779	10	0	0
T7	3272	14	0	0
T8	2681	10	0	0
T9	2318	14	0	0
T10	4435	5	0	0
T37	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	28651	0	0
T1	10108	6	0	0
T2	2170	5	0	0
T3	18007	46	0	0
T4	7089	19	0	0
T5	1265	3	0	0
T6	14779	10	0	0
T7	3272	14	0	0
T8	2681	10	0	0
T9	2318	15	0	0
T10	4435	6	0	0