Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	15907153	13420	0	0
EscTimeoutStoppedByClReset_A	15906564	2228942	0	0
EscTimeoutTriggersReset_A	3519646	471	0	0
RomAllowActiveState_A	15906564	40809	0	0
RomAllowCheckGoodState_A	15906564	40863	0	0
RomBlockActiveState_A	15906564	24979	0	0
RomBlockCheckGoodState_A	15906564	345653	0	0
RomIntgChkDisFalse_A	15906564	15398384	0	0
RomIntgChkDisTrue_A	15906564	120381	0	0
RstreqChkEsctimeout_A	15906564	2950	0	0
RstreqChkFsmterm_A	15906564	140	0	0
RstreqChkGlbesc_A	15906564	2950	0	0
RstreqChkMainpd_A	15906564	701063	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15907153	13420	0	0
T11	10975	487	0	0
T12	2419	0	0	0
T16	3075	0	0	0
T17	1100	0	0	0
T22	286205	0	0	0
T24	35404	0	0	0
T25	1384	0	0	0
T33	0	407	0	0
T34	0	34	0	0
T38	2544	0	0	0
T41	1440	0	0	0
T134	0	507	0	0
T135	0	179	0	0
T136	0	264	0	0
T137	0	9	0	0
T138	0	154	0	0
T139	0	384	0	0
T140	0	34	0	0
T141	4825	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	2228942	0	0
T1	10108	2822	0	0
T2	2170	52	0	0
T3	18007	3453	0	0
T4	7089	376	0	0
T5	1265	36	0	0
T6	14779	2620	0	0
T7	3272	0	0	0
T8	2681	0	0	0
T9	2318	317	0	0
T10	4435	612	0	0
T15	0	16	0	0
T37	0	9	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3519646	471	0	0
T11	153	6	0	0
T12	214	3	0	0
T13	0	3	0	0
T16	306	0	0	0
T17	616	0	0	0
T22	27564	0	0	0
T24	7047	0	0	0
T25	499	0	0	0
T33	0	5	0	0
T34	0	5	0	0
T38	775	0	0	0
T41	508	0	0	0
T93	0	2	0	0
T134	0	6	0	0
T135	0	5	0	0
T136	0	6	0	0
T141	368	0	0	0
T142	0	4	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	40809	0	0
T1	10108	10	0	0
T2	2170	5	0	0
T3	18007	84	0	0
T4	7089	12	0	0
T5	1265	3	0	0
T6	14779	15	0	0
T7	3272	21	0	0
T8	2681	15	0	0
T9	2318	15	0	0
T10	4435	7	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	40863	0	0
T1	10108	10	0	0
T2	2170	5	0	0
T3	18007	84	0	0
T4	7089	13	0	0
T5	1265	3	0	0
T6	14779	15	0	0
T7	3272	21	0	0
T8	2681	15	0	0
T9	2318	15	0	0
T10	4435	7	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	24979	0	0
T3	18007	2	0	0
T4	7089	0	0	0
T5	1265	0	0	0
T6	14779	0	0	0
T7	3272	0	0	0
T8	2681	0	0	0
T9	2318	0	0	0
T10	4435	0	0	0
T15	1621	0	0	0
T25	0	187	0	0
T37	2087	0	0	0
T43	0	7	0	0
T84	0	8	0	0
T89	0	936	0	0
T143	0	17	0	0
T144	0	3	0	0
T145	0	9	0	0
T146	0	447	0	0
T147	0	181	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	345653	0	0
T3	18007	1367	0	0
T4	7089	0	0	0
T5	1265	0	0	0
T6	14779	0	0	0
T7	3272	0	0	0
T8	2681	0	0	0
T9	2318	0	0	0
T10	4435	0	0	0
T14	0	2206	0	0
T15	1621	0	0	0
T21	0	804	0	0
T22	0	2478	0	0
T23	0	4009	0	0
T24	0	2236	0	0
T25	0	58	0	0
T28	0	115	0	0
T29	0	23	0	0
T30	0	92	0	0
T37	2087	0	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	15398384	0	0
T1	10108	10009	0	0
T2	2170	1773	0	0
T3	18007	17863	0	0
T4	7089	6218	0	0
T5	1265	1074	0	0
T6	14779	14693	0	0
T7	3272	3198	0	0
T8	2681	2583	0	0
T9	2318	2252	0	0
T10	4435	4336	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	120381	0	0
T11	10974	0	0	0
T14	97642	0	0	0
T16	3075	0	0	0
T21	47967	0	0	0
T23	47007	2789	0	0
T24	35404	1564	0	0
T25	1384	34	0	0
T35	3387	0	0	0
T36	3318	0	0	0
T72	1328	0	0	0
T84	0	247	0	0
T85	0	373	0	0
T89	0	436	0	0
T143	0	557	0	0
T147	0	1058	0	0
T148	0	1205	0	0
T149	0	965	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	2950	0	0
T4	7089	5	0	0
T5	1265	2	0	0
T6	14779	0	0	0
T7	3272	0	0	0
T8	2681	0	0	0
T9	2318	6	0	0
T10	4435	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	0	35	0	0
T15	1621	0	0	0
T22	0	55	0	0
T23	47007	0	0	0
T25	0	3	0	0
T35	0	6	0	0
T36	0	7	0	0
T37	2087	0	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	140	0	0
T13	2360	0	0	0
T18	14226	40	0	0
T19	46774	40	0	0
T20	0	20	0	0
T26	0	20	0	0
T27	0	20	0	0
T28	27597	0	0	0
T29	134684	0	0	0
T30	3007	0	0	0
T31	2253	0	0	0
T32	75292	0	0	0
T33	10682	0	0	0
T34	9195	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	2950	0	0
T4	7089	5	0	0
T5	1265	2	0	0
T6	14779	0	0	0
T7	3272	0	0	0
T8	2681	0	0	0
T9	2318	6	0	0
T10	4435	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	0	35	0	0
T15	1621	0	0	0
T22	0	55	0	0
T23	47007	0	0	0
T25	0	3	0	0
T35	0	6	0	0
T36	0	7	0	0
T37	2087	0	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15906564	701063	0	0
T3	18007	1378	0	0
T4	7089	161	0	0
T5	1265	0	0	0
T6	14779	0	0	0
T7	3272	0	0	0
T8	2681	0	0	0
T9	2318	171	0	0
T10	4435	0	0	0
T14	0	4862	0	0
T15	1621	27	0	0
T21	0	882	0	0
T23	0	4628	0	0
T24	0	2520	0	0
T35	0	167	0	0
T36	0	577	0	0
T37	2087	0	0	0