Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	367388	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

148076

1

T2

1

T3

22

T4

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	271730	1			T1	1		T2	1		T3	42
values[0x0]	121533	1			T3	16		T4	22		T5	226
values[0x1]	122201	1			T3	24		T4	20		T5	226

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	291007	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

224457

1

T2

1

T3

30

T4

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1603	1			T4	5		T26	10		T46	2
valid_sources[0x01]	3503	1			T12	3		T25	4		T86	1
valid_sources[0x02]	1760	1			T48	1		T39	3		T86	1
valid_sources[0x03]	3498	1			T3	1		T48	1		T39	3
valid_sources[0x04]	1558	1			T25	7		T14	3		T26	11
valid_sources[0x05]	1585	1			T86	3		T26	10		T46	3
valid_sources[0x06]	1655	1			T7	4		T8	29		T13	4
valid_sources[0x07]	1638	1			T3	1		T7	1		T8	8
valid_sources[0x08]	1916	1			T7	1		T13	2		T25	18
valid_sources[0x09]	2179	1			T3	1		T14	1		T26	1
valid_sources[0x0a]	1623	1			T3	1		T7	1		T86	1
valid_sources[0x0b]	1618	1			T26	7		T46	1		T21	13
valid_sources[0x0c]	1522	1			T4	4		T12	1		T48	1
valid_sources[0x0d]	1663	1			T3	2		T25	5		T86	1
valid_sources[0x0e]	1741	1			T10	1		T13	6		T25	4
valid_sources[0x0f]	1770	1			T3	1		T4	1		T58	4
valid_sources[0x10]	1654	1			T4	1		T48	1		T25	7
valid_sources[0x11]	1546	1			T39	2		T58	2		T49	1
valid_sources[0x12]	2004	1			T10	1		T39	3		T26	5
valid_sources[0x13]	2887	1			T13	1		T86	1		T26	10
valid_sources[0x14]	1679	1			T7	1		T58	2		T26	8
valid_sources[0x15]	1790	1			T3	1		T4	1		T13	5
valid_sources[0x16]	4081	1			T10	1		T86	1		T26	14
valid_sources[0x17]	2086	1			T3	1		T4	1		T48	1
valid_sources[0x18]	1872	1			T25	6		T86	1		T14	1
valid_sources[0x19]	1551	1			T86	4		T26	8		T21	7
valid_sources[0x1a]	3729	1			T10	1		T48	1		T13	1
valid_sources[0x1b]	1759	1			T3	4		T13	2		T25	1
valid_sources[0x1c]	1458	1			T13	1		T25	6		T86	3
valid_sources[0x1d]	2630	1			T3	2		T86	1		T58	1
valid_sources[0x1e]	1608	1			T25	4		T58	1		T26	10
valid_sources[0x1f]	1550	1			T86	1		T26	10		T21	25
valid_sources[0x20]	5187	1			T4	1		T13	4		T49	1
valid_sources[0x21]	1599	1			T24	7		T48	1		T13	3
valid_sources[0x22]	1427	1			T86	1		T58	3		T14	1
valid_sources[0x23]	1445	1			T13	2		T86	1		T26	7
valid_sources[0x24]	1984	1			T48	1		T86	2		T14	1
valid_sources[0x25]	1773	1			T4	2		T26	7		T21	6
valid_sources[0x26]	1558	1			T25	4		T58	2		T26	18
valid_sources[0x27]	1675	1			T4	1		T48	1		T86	2
valid_sources[0x28]	1816	1			T12	1		T48	1		T25	5
valid_sources[0x29]	2061	1			T86	1		T14	1		T26	9
valid_sources[0x2a]	1688	1			T10	2		T39	1		T86	2
valid_sources[0x2b]	1859	1			T3	3		T48	1		T26	17
valid_sources[0x2c]	1852	1			T3	1		T48	1		T25	18
valid_sources[0x2d]	4448	1			T48	1		T86	1		T26	7
valid_sources[0x2e]	1620	1			T24	3		T13	4		T86	1
valid_sources[0x2f]	1742	1			T3	2		T7	1		T13	1
valid_sources[0x30]	4954	1			T4	3		T13	1		T86	1
valid_sources[0x31]	1691	1			T4	1		T25	7		T58	14
valid_sources[0x32]	1766	1			T86	1		T58	1		T14	1
valid_sources[0x33]	1770	1			T12	3		T39	13		T86	2
valid_sources[0x34]	1685	1			T4	1		T13	2		T25	5
valid_sources[0x35]	2280	1			T48	1		T86	1		T49	2
valid_sources[0x36]	1785	1			T10	1		T24	4		T86	1
valid_sources[0x37]	1540	1			T3	1		T25	15		T39	2
valid_sources[0x38]	1476	1			T25	29		T86	1		T58	1
valid_sources[0x39]	1840	1			T26	11		T46	2		T21	1
valid_sources[0x3a]	2013	1			T10	1		T13	6		T39	2
valid_sources[0x3b]	1532	1			T12	1		T25	15		T86	3
valid_sources[0x3c]	2730	1			T3	1		T7	2		T25	5
valid_sources[0x3d]	1471	1			T13	3		T26	4		T46	2
valid_sources[0x3e]	1843	1			T12	1		T13	16		T25	23
valid_sources[0x3f]	1511	1			T26	4		T65	14		T21	3
valid_sources[0x40]	1920	1			T7	4		T86	2		T26	12
valid_sources[0x41]	1632	1			T48	1		T86	2		T26	14
valid_sources[0x42]	2582	1			T48	1		T25	7		T26	2
valid_sources[0x43]	1520	1			T3	1		T86	3		T26	9
valid_sources[0x44]	1756	1			T24	1		T25	2		T58	1
valid_sources[0x45]	2504	1			T5	858		T48	1		T86	1
valid_sources[0x46]	1885	1			T3	2		T4	3		T13	2
valid_sources[0x47]	1486	1			T3	2		T13	1		T58	1
valid_sources[0x48]	1855	1			T4	3		T13	4		T39	12
valid_sources[0x49]	1497	1			T7	1		T48	1		T39	5
valid_sources[0x4a]	1545	1			T7	2		T39	1		T86	1
valid_sources[0x4b]	1785	1			T7	1		T86	1		T14	1
valid_sources[0x4c]	3108	1			T58	3		T49	1		T26	6
valid_sources[0x4d]	1674	1			T2	1		T4	1		T48	1
valid_sources[0x4e]	1891	1			T4	1		T25	8		T39	6
valid_sources[0x4f]	1894	1			T3	1		T13	5		T39	6
valid_sources[0x50]	2712	1			T4	2		T10	1		T25	23
valid_sources[0x51]	1882	1			T13	5		T26	9		T46	1
valid_sources[0x52]	1982	1			T58	1		T26	6		T27	76
valid_sources[0x53]	1447	1			T3	2		T86	1		T14	2
valid_sources[0x54]	1775	1			T10	1		T25	17		T39	4
valid_sources[0x55]	2453	1			T58	1		T26	10		T85	1
valid_sources[0x56]	1980	1			T13	4		T25	8		T86	2
valid_sources[0x57]	1638	1			T25	34		T14	1		T26	10
valid_sources[0x58]	1724	1			T25	23		T39	1		T86	2
valid_sources[0x59]	2035	1			T4	3		T25	10		T86	1
valid_sources[0x5a]	1867	1			T48	1		T13	4		T25	30
valid_sources[0x5b]	1592	1			T86	3		T26	9		T46	1
valid_sources[0x5c]	1525	1			T13	3		T86	1		T49	1
valid_sources[0x5d]	1524	1			T13	10		T58	2		T26	13
valid_sources[0x5e]	1453	1			T3	1		T86	2		T26	20
valid_sources[0x5f]	1530	1			T24	1		T48	1		T13	2
valid_sources[0x60]	2029	1			T3	1		T4	4		T48	1
valid_sources[0x61]	1616	1			T3	1		T4	3		T48	1
valid_sources[0x62]	1702	1			T13	7		T14	1		T26	12
valid_sources[0x63]	1709	1			T3	1		T13	4		T39	3
valid_sources[0x64]	2409	1			T4	2		T13	3		T86	2
valid_sources[0x65]	1593	1			T25	3		T39	6		T86	3
valid_sources[0x66]	1697	1			T4	2		T13	1		T86	1
valid_sources[0x67]	1623	1			T7	4		T48	2		T86	2
valid_sources[0x68]	2605	1			T25	19		T86	1		T26	3
valid_sources[0x69]	2991	1			T39	1		T49	1		T14	2
valid_sources[0x6a]	1508	1			T3	1		T7	1		T86	3
valid_sources[0x6b]	2103	1			T86	2		T58	2		T14	1
valid_sources[0x6c]	2196	1			T3	1		T4	9		T48	1
valid_sources[0x6d]	1601	1			T4	2		T13	7		T25	1
valid_sources[0x6e]	2760	1			T3	2		T86	2		T14	1
valid_sources[0x6f]	2003	1			T3	2		T25	7		T39	1
valid_sources[0x70]	1771	1			T86	1		T58	1		T26	8
valid_sources[0x71]	1617	1			T4	3		T86	1		T26	5
valid_sources[0x72]	1622	1			T26	14		T46	3		T21	28
valid_sources[0x73]	1507	1			T25	3		T86	2		T26	11
valid_sources[0x74]	2313	1			T39	9		T86	3		T26	9
valid_sources[0x75]	1564	1			T3	1		T58	2		T26	5
valid_sources[0x76]	2845	1			T48	2		T25	3		T39	9
valid_sources[0x77]	1770	1			T12	3		T13	1		T25	21
valid_sources[0x78]	1804	1			T48	1		T25	17		T86	2
valid_sources[0x79]	1869	1			T25	7		T86	1		T14	1
valid_sources[0x7a]	1628	1			T13	9		T49	1		T26	10
valid_sources[0x7b]	1581	1			T11	1		T86	3		T49	3
valid_sources[0x7c]	3384	1			T24	2		T25	40		T86	1
valid_sources[0x7d]	1862	1			T3	1		T7	1		T86	1
valid_sources[0x7e]	1539	1			T86	2		T58	1		T26	26
valid_sources[0x7f]	1474	1			T86	3		T58	6		T26	15
valid_sources[0x80]	2440	1			T86	2		T26	22		T46	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75707

1

T2

1

T3

14

T4

10

values[0x0]

all_enables

biggest_size

46325

1

T3

2

T4

9

T5

72

values[0x1]

all_enables

biggest_size

26044

1

T3

6

T4

5

T5

31