SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34996 | 1 | T5 | 317 | T134 | 372 | T22 | 1 | ||||
others[1] | 35074 | 1 | T5 | 305 | T27 | 1 | T134 | 418 | ||||
others[2] | 34944 | 1 | T5 | 290 | T134 | 411 | T138 | 444 | ||||
others[3] | 58230 | 1 | T5 | 502 | T134 | 649 | T22 | 1 | ||||
false | 13637 | 1 | T5 | 50 | T8 | 3 | T24 | 4 | ||||
true | 22134 | 1 | T1 | 5 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34817 | 1 | T5 | 279 | T134 | 362 | T22 | 1 | ||||
others[1] | 35344 | 1 | T5 | 293 | T134 | 441 | T138 | 377 | ||||
others[2] | 35273 | 1 | T5 | 309 | T27 | 1 | T134 | 397 | ||||
others[3] | 57986 | 1 | T5 | 520 | T50 | 1 | T134 | 652 | ||||
false | 9462 | 1 | T5 | 50 | T8 | 5 | T24 | 2 | ||||
true | 18008 | 1 | T1 | 5 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 542 | 1 | T4 | 2 | T7 | 1 | T40 | 1 | ||||
others[1] | 556 | 1 | T4 | 1 | T7 | 2 | T40 | 1 | ||||
others[2] | 549 | 1 | T4 | 1 | T7 | 1 | T25 | 1 | ||||
others[3] | 885 | 1 | T4 | 1 | T25 | 4 | T39 | 3 | ||||
false | 10129 | 1 | T1 | 5 | T2 | 2 | T3 | 1 | ||||
true | 2687 | 1 | T4 | 2 | T7 | 4 | T8 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |