Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	17375576	14515	0	0
intr_enable_rd_A	17375576	28370	0	0
reset_en_rd_A	17375576	1540	0	0
reset_en_regwen_rd_A	17375576	1283	0	0
wake_info_capture_dis_rd_A	17375576	1251	0	0
wakeup_en_rd_A	17375576	2704	0	0
wakeup_en_regwen_rd_A	17375576	1225	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17375576	14515	0	0
T21	142300	17	0	0
T22	92149	3	0	0
T23	0	61	0	0
T50	5031	0	0	0
T51	0	96	0	0
T54	0	22	0	0
T55	0	43	0	0
T66	9338	0	0	0
T73	0	66	0	0
T131	0	12	0	0
T132	0	4	0	0
T133	0	33	0	0
T134	24410	0	0	0
T135	895	0	0	0
T136	15247	0	0	0
T137	4100	0	0	0
T138	22253	0	0	0
T139	9531	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17375576	28370	0	0
T4	4000	40	0	0
T5	51164	147	0	0
T6	10073	0	0	0
T7	3236	0	0	0
T8	2353	9	0	0
T9	1885	0	0	0
T10	1696	0	0	0
T11	821	0	0	0
T12	2634	7	0	0
T21	0	646	0	0
T24	2389	0	0	0
T40	0	196	0	0
T64	0	36	0	0
T70	0	42	0	0
T134	0	107	0	0
T137	0	33	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17375576	1540	0	0
T21	142300	23	0	0
T22	92149	9	0	0
T50	5031	0	0	0
T55	0	23	0	0
T59	0	12	0	0
T66	9338	0	0	0
T88	0	23	0	0
T131	0	12	0	0
T132	0	7	0	0
T134	24410	0	0	0
T135	895	0	0	0
T136	15247	0	0	0
T137	4100	0	0	0
T138	22253	0	0	0
T139	9531	0	0	0
T140	0	13	0	0
T141	0	14	0	0
T142	0	4	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17375576	1283	0	0
T21	142300	15	0	0
T22	92149	17	0	0
T50	5031	0	0	0
T55	0	16	0	0
T59	0	16	0	0
T66	9338	0	0	0
T88	0	19	0	0
T131	0	9	0	0
T132	0	10	0	0
T134	24410	0	0	0
T135	895	0	0	0
T136	15247	0	0	0
T137	4100	0	0	0
T138	22253	0	0	0
T139	9531	0	0	0
T140	0	16	0	0
T141	0	8	0	0
T142	0	18	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17375576	1251	0	0
T21	142300	11	0	0
T22	92149	3	0	0
T50	5031	0	0	0
T55	0	15	0	0
T59	0	17	0	0
T66	9338	0	0	0
T88	0	29	0	0
T131	0	2	0	0
T132	0	7	0	0
T134	24410	0	0	0
T135	895	0	0	0
T136	15247	0	0	0
T137	4100	0	0	0
T138	22253	0	0	0
T139	9531	0	0	0
T140	0	16	0	0
T141	0	10	0	0
T143	0	17	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17375576	2704	0	0
T21	142300	18	0	0
T22	92149	14	0	0
T50	5031	0	0	0
T55	0	19	0	0
T59	0	11	0	0
T66	9338	0	0	0
T88	0	18	0	0
T131	0	6	0	0
T132	0	9	0	0
T134	24410	0	0	0
T135	895	0	0	0
T136	15247	0	0	0
T137	4100	0	0	0
T138	22253	0	0	0
T139	9531	0	0	0
T140	0	17	0	0
T141	0	15	0	0
T142	0	13	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17375576	1225	0	0
T21	142300	16	0	0
T22	92149	14	0	0
T50	5031	0	0	0
T55	0	38	0	0
T59	0	4	0	0
T66	9338	0	0	0
T88	0	30	0	0
T131	0	4	0	0
T132	0	14	0	0
T134	24410	0	0	0
T135	895	0	0	0
T136	15247	0	0	0
T137	4100	0	0	0
T138	22253	0	0	0
T139	9531	0	0	0
T140	0	10	0	0
T141	0	12	0	0
T142	0	24	0	0