Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	50459850	101281	0	0
StatusRise_A	50459850	114033	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50459850	101281	0	0
T2	6669	3	0	0
T3	3192	15	0	0
T4	12000	42	0	0
T5	153492	209	0	0
T6	30219	12	0	0
T7	9708	54	0	0
T8	7059	15	0	0
T9	5655	0	0	0
T10	5088	12	0	0
T11	0	3	0	0
T12	7902	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50459850	114033	0	0
T1	4599	15	0	0
T2	6669	9	0	0
T3	3192	17	0	0
T4	12000	45	0	0
T5	153492	212	0	0
T6	30219	15	0	0
T7	9708	60	0	0
T8	7059	18	0	0
T9	5655	6	0	0
T10	5088	15	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16819950	37725	0	0
StatusRise_A	16819950	42277	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	37725	0	0
T2	2223	1	0	0
T3	1064	5	0	0
T4	4000	14	0	0
T5	51164	83	0	0
T6	10073	4	0	0
T7	3236	18	0	0
T8	2353	5	0	0
T9	1885	0	0	0
T10	1696	4	0	0
T11	0	1	0	0
T12	2634	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	42277	0	0
T1	1533	5	0	0
T2	2223	3	0	0
T3	1064	6	0	0
T4	4000	15	0	0
T5	51164	84	0	0
T6	10073	5	0	0
T7	3236	20	0	0
T8	2353	6	0	0
T9	1885	2	0	0
T10	1696	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16819950	37725	0	0
StatusRise_A	16819950	42280	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	37725	0	0
T2	2223	1	0	0
T3	1064	5	0	0
T4	4000	14	0	0
T5	51164	83	0	0
T6	10073	4	0	0
T7	3236	18	0	0
T8	2353	5	0	0
T9	1885	0	0	0
T10	1696	4	0	0
T11	0	1	0	0
T12	2634	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	42280	0	0
T1	1533	5	0	0
T2	2223	3	0	0
T3	1064	6	0	0
T4	4000	15	0	0
T5	51164	84	0	0
T6	10073	5	0	0
T7	3236	20	0	0
T8	2353	6	0	0
T9	1885	2	0	0
T10	1696	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16819950	25831	0	0
StatusRise_A	16819950	29476	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	25831	0	0
T2	2223	1	0	0
T3	1064	5	0	0
T4	4000	14	0	0
T5	51164	43	0	0
T6	10073	4	0	0
T7	3236	18	0	0
T8	2353	5	0	0
T9	1885	0	0	0
T10	1696	4	0	0
T11	0	1	0	0
T12	2634	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	29476	0	0
T1	1533	5	0	0
T2	2223	3	0	0
T3	1064	5	0	0
T4	4000	15	0	0
T5	51164	44	0	0
T6	10073	5	0	0
T7	3236	20	0	0
T8	2353	6	0	0
T9	1885	2	0	0
T10	1696	5	0	0