Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	16820550	10906	0	0
EscTimeoutStoppedByClReset_A	16819950	2358572	0	0
EscTimeoutTriggersReset_A	3646484	429	0	0
RomAllowActiveState_A	16819950	41850	0	0
RomAllowCheckGoodState_A	16819950	41900	0	0
RomBlockActiveState_A	16819950	29848	0	0
RomBlockCheckGoodState_A	16819950	344739	0	0
RomIntgChkDisFalse_A	16819950	16261697	0	0
RomIntgChkDisTrue_A	16819950	154916	0	0
RstreqChkEsctimeout_A	16819950	2934	0	0
RstreqChkFsmterm_A	16819950	180	0	0
RstreqChkGlbesc_A	16819950	2934	0	0
RstreqChkMainpd_A	16819950	682994	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16820550	10906	0	0
T6	10074	260	0	0
T7	3236	0	0	0
T8	2354	0	0	0
T9	1885	0	0	0
T10	1697	0	0	0
T11	822	7	0	0
T12	2634	0	0	0
T13	2029	0	0	0
T24	2390	0	0	0
T42	0	366	0	0
T43	0	24	0	0
T48	2938	0	0	0
T93	0	5	0	0
T139	0	83	0	0
T146	0	17	0	0
T147	0	4	0	0
T148	0	79	0	0
T149	0	374	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	2358572	0	0
T1	1533	40	0	0
T2	2223	22	0	0
T3	1064	13	0	0
T4	4000	491	0	0
T5	51164	8453	0	0
T6	10073	48	0	0
T7	3236	365	0	0
T8	2353	112	0	0
T9	1885	0	0	0
T10	1696	70	0	0
T12	0	13	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3646484	429	0	0
T2	209	3	0	0
T3	554	0	0	0
T4	580	0	0	0
T5	6169	0	0	0
T6	214	5	0	0
T7	1184	0	0	0
T8	676	0	0	0
T9	166	0	0	0
T10	621	0	0	0
T11	0	5	0	0
T12	222	0	0	0
T20	0	5	0	0
T42	0	5	0	0
T43	0	3	0	0
T44	0	4	0	0
T146	0	7	0	0
T147	0	5	0	0
T148	0	5	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	41850	0	0
T1	1533	5	0	0
T2	2223	3	0	0
T3	1064	6	0	0
T4	4000	15	0	0
T5	51164	84	0	0
T6	10073	5	0	0
T7	3236	13	0	0
T8	2353	6	0	0
T9	1885	2	0	0
T10	1696	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	41900	0	0
T1	1533	5	0	0
T2	2223	3	0	0
T3	1064	6	0	0
T4	4000	15	0	0
T5	51164	84	0	0
T6	10073	5	0	0
T7	3236	14	0	0
T8	2353	6	0	0
T9	1885	2	0	0
T10	1696	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	29848	0	0
T8	2353	300	0	0
T9	1885	0	0	0
T10	1696	0	0	0
T11	821	0	0	0
T12	2634	0	0	0
T13	2029	0	0	0
T20	789	0	0	0
T24	2389	0	0	0
T25	27514	0	0	0
T27	0	799	0	0
T48	2938	0	0	0
T50	0	1060	0	0
T138	0	20	0	0
T150	0	683	0	0
T151	0	3	0	0
T152	0	3	0	0
T153	0	2	0	0
T154	0	679	0	0
T155	0	106	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	344739	0	0
T5	51164	3407	0	0
T6	10073	0	0	0
T7	3236	0	0	0
T8	2353	106	0	0
T9	1885	0	0	0
T10	1696	0	0	0
T11	821	0	0	0
T12	2634	0	0	0
T21	0	505	0	0
T24	2389	45	0	0
T25	0	759	0	0
T26	0	598	0	0
T27	0	610	0	0
T40	0	618	0	0
T48	2938	0	0	0
T50	0	941	0	0
T134	0	1336	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	16261697	0	0
T1	1533	1201	0	0
T2	2223	2044	0	0
T3	1064	1001	0	0
T4	4000	3926	0	0
T5	51164	49327	0	0
T6	10073	10000	0	0
T7	3236	2260	0	0
T8	2353	1281	0	0
T9	1885	1721	0	0
T10	1696	1336	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	154916	0	0
T5	51164	1739	0	0
T6	10073	0	0	0
T7	3236	0	0	0
T8	2353	1003	0	0
T9	1885	0	0	0
T10	1696	0	0	0
T11	821	0	0	0
T12	2634	0	0	0
T24	2389	0	0	0
T27	0	184	0	0
T48	2938	0	0	0
T50	0	563	0	0
T150	0	1043	0	0
T151	0	197	0	0
T152	0	233	0	0
T154	0	106	0	0
T155	0	185	0	0
T156	0	1920	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	2934	0	0
T1	1533	4	0	0
T2	2223	1	0	0
T3	1064	0	0	0
T4	4000	5	0	0
T5	51164	0	0	0
T6	10073	2	0	0
T7	3236	4	0	0
T8	2353	2	0	0
T9	1885	0	0	0
T10	1696	0	0	0
T11	0	1	0	0
T20	0	1	0	0
T25	0	7	0	0
T39	0	5	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	180	0	0
T17	9177	20	0	0
T18	0	40	0	0
T19	0	40	0	0
T28	0	40	0	0
T29	0	40	0	0
T30	2698	0	0	0
T31	746	0	0	0
T32	4635	0	0	0
T33	7062	0	0	0
T34	7213	0	0	0
T35	2880	0	0	0
T36	54017	0	0	0
T37	87508	0	0	0
T38	4243	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	2934	0	0
T1	1533	4	0	0
T2	2223	1	0	0
T3	1064	0	0	0
T4	4000	5	0	0
T5	51164	0	0	0
T6	10073	2	0	0
T7	3236	4	0	0
T8	2353	2	0	0
T9	1885	0	0	0
T10	1696	0	0	0
T11	0	1	0	0
T20	0	1	0	0
T25	0	7	0	0
T39	0	5	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16819950	682994	0	0
T4	4000	521	0	0
T5	51164	5591	0	0
T6	10073	0	0	0
T7	3236	162	0	0
T8	2353	50	0	0
T9	1885	6	0	0
T10	1696	0	0	0
T11	821	0	0	0
T12	2634	0	0	0
T24	2389	185	0	0
T25	0	1236	0	0
T39	0	91	0	0
T40	0	515	0	0
T41	0	100	0	0