Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	353082	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

143027

1

T1

68

T2

27

T3

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	262314	1			T1	114		T2	182		T3	64
values[0x0]	116616	1			T1	67		T2	41		T3	2
values[0x1]	117179	1			T1	74		T2	21		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	279522	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

216587

1

T1

109

T2

85

T3

42

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1819	1			T7	3		T8	4		T10	1
valid_sources[0x01]	1687	1			T1	14		T7	7		T8	5
valid_sources[0x02]	2830	1			T8	24		T37	29		T38	9
valid_sources[0x03]	1694	1			T4	2		T7	3		T8	14
valid_sources[0x04]	2259	1			T39	1		T12	1		T14	14
valid_sources[0x05]	2562	1			T3	2		T7	5		T10	1
valid_sources[0x06]	1912	1			T7	6		T8	11		T14	11
valid_sources[0x07]	1585	1			T7	1		T8	10		T36	1
valid_sources[0x08]	2871	1			T3	1		T7	1		T8	9
valid_sources[0x09]	1496	1			T3	1		T7	3		T8	10
valid_sources[0x0a]	2991	1			T7	8		T10	1		T36	2
valid_sources[0x0b]	1849	1			T8	19		T10	2		T39	2
valid_sources[0x0c]	2160	1			T7	5		T8	2		T10	1
valid_sources[0x0d]	1631	1			T6	29		T38	4		T87	1
valid_sources[0x0e]	1684	1			T7	12		T8	4		T10	2
valid_sources[0x0f]	1625	1			T4	9		T8	19		T10	1
valid_sources[0x10]	1618	1			T7	5		T8	7		T10	3
valid_sources[0x11]	1584	1			T7	1		T8	3		T10	1
valid_sources[0x12]	1581	1			T7	5		T8	37		T36	8
valid_sources[0x13]	1527	1			T8	3		T10	1		T35	2
valid_sources[0x14]	1602	1			T3	2		T7	1		T39	2
valid_sources[0x15]	1582	1			T7	1		T36	2		T37	12
valid_sources[0x16]	1448	1			T7	1		T8	8		T36	1
valid_sources[0x17]	1602	1			T3	1		T7	4		T10	2
valid_sources[0x18]	1551	1			T7	15		T8	11		T36	3
valid_sources[0x19]	2106	1			T7	2		T8	5		T10	1
valid_sources[0x1a]	2705	1			T7	6		T38	8		T74	3
valid_sources[0x1b]	2799	1			T3	1		T7	5		T8	17
valid_sources[0x1c]	1759	1			T7	3		T36	1		T38	1
valid_sources[0x1d]	1737	1			T7	2		T8	3		T36	2
valid_sources[0x1e]	1684	1			T7	4		T8	6		T36	7
valid_sources[0x1f]	2434	1			T8	8		T10	1		T36	2
valid_sources[0x20]	1586	1			T7	3		T8	8		T39	3
valid_sources[0x21]	2525	1			T7	3		T8	15		T10	1
valid_sources[0x22]	1869	1			T7	3		T8	13		T10	2
valid_sources[0x23]	3129	1			T7	6		T8	14		T9	879
valid_sources[0x24]	1667	1			T8	14		T10	1		T38	12
valid_sources[0x25]	1877	1			T7	17		T36	3		T37	3
valid_sources[0x26]	2965	1			T7	9		T8	15		T38	4
valid_sources[0x27]	1594	1			T7	6		T8	14		T36	9
valid_sources[0x28]	1447	1			T7	17		T8	6		T36	1
valid_sources[0x29]	1671	1			T8	11		T10	1		T36	3
valid_sources[0x2a]	1670	1			T7	3		T8	8		T10	1
valid_sources[0x2b]	1787	1			T8	3		T36	8		T13	1
valid_sources[0x2c]	1486	1			T1	31		T7	5		T8	3
valid_sources[0x2d]	1522	1			T8	14		T38	7		T74	1
valid_sources[0x2e]	1555	1			T7	2		T8	11		T36	4
valid_sources[0x2f]	1647	1			T3	5		T7	1		T8	14
valid_sources[0x30]	1512	1			T8	1		T10	1		T38	7
valid_sources[0x31]	1675	1			T8	3		T36	2		T37	11
valid_sources[0x32]	1883	1			T7	2		T8	9		T10	2
valid_sources[0x33]	2019	1			T7	3		T38	5		T87	2
valid_sources[0x34]	2055	1			T7	5		T8	11		T10	1
valid_sources[0x35]	2473	1			T2	244		T7	4		T8	2
valid_sources[0x36]	3390	1			T8	26		T36	8		T37	16
valid_sources[0x37]	1637	1			T7	3		T8	9		T10	2
valid_sources[0x38]	1719	1			T8	9		T36	2		T38	5
valid_sources[0x39]	1470	1			T4	5		T7	3		T8	14
valid_sources[0x3a]	1738	1			T7	2		T8	5		T36	4
valid_sources[0x3b]	2270	1			T7	3		T35	1		T38	4
valid_sources[0x3c]	1430	1			T7	1		T10	1		T35	2
valid_sources[0x3d]	1598	1			T3	2		T7	1		T10	5
valid_sources[0x3e]	2405	1			T7	5		T8	18		T10	1
valid_sources[0x3f]	1628	1			T8	5		T35	1		T36	6
valid_sources[0x40]	1439	1			T7	1		T8	5		T10	2
valid_sources[0x41]	1858	1			T3	2		T7	1		T8	23
valid_sources[0x42]	1524	1			T7	3		T8	7		T10	1
valid_sources[0x43]	2857	1			T7	8		T8	3		T10	3
valid_sources[0x44]	2715	1			T8	41		T10	2		T37	11
valid_sources[0x45]	3590	1			T8	10		T10	2		T38	6
valid_sources[0x46]	1948	1			T3	2		T8	11		T10	1
valid_sources[0x47]	2186	1			T7	1		T10	1		T38	5
valid_sources[0x48]	1527	1			T7	2		T8	1		T10	3
valid_sources[0x49]	1645	1			T7	8		T10	1		T36	3
valid_sources[0x4a]	2030	1			T7	2		T8	24		T36	14
valid_sources[0x4b]	2359	1			T8	15		T10	1		T39	2
valid_sources[0x4c]	1464	1			T8	31		T36	4		T14	19
valid_sources[0x4d]	3049	1			T8	4		T36	2		T14	12
valid_sources[0x4e]	1715	1			T7	1		T36	1		T38	3
valid_sources[0x4f]	1715	1			T7	3		T8	17		T37	1
valid_sources[0x50]	2463	1			T7	1		T36	9		T37	3
valid_sources[0x51]	1596	1			T10	1		T36	4		T14	11
valid_sources[0x52]	1653	1			T4	20		T7	12		T14	13
valid_sources[0x53]	2607	1			T7	7		T8	12		T36	1
valid_sources[0x54]	1594	1			T7	2		T8	24		T36	3
valid_sources[0x55]	1458	1			T8	11		T36	15		T38	4
valid_sources[0x56]	2895	1			T8	2		T14	1168		T37	34
valid_sources[0x57]	1793	1			T3	4		T7	5		T8	1
valid_sources[0x58]	1419	1			T8	5		T10	1		T38	9
valid_sources[0x59]	1746	1			T7	11		T8	3		T10	2
valid_sources[0x5a]	1652	1			T7	1		T8	7		T14	11
valid_sources[0x5b]	2508	1			T1	12		T3	1		T8	3
valid_sources[0x5c]	1918	1			T7	7		T14	262		T38	13
valid_sources[0x5d]	1534	1			T7	3		T8	2		T37	25
valid_sources[0x5e]	1522	1			T7	4		T10	4		T36	2
valid_sources[0x5f]	1991	1			T8	3		T10	4		T36	5
valid_sources[0x60]	1695	1			T7	8		T8	16		T36	2
valid_sources[0x61]	1427	1			T7	3		T8	20		T10	1
valid_sources[0x62]	1574	1			T7	2		T8	4		T10	5
valid_sources[0x63]	4213	1			T7	2		T8	25		T36	3
valid_sources[0x64]	1882	1			T10	2		T36	3		T38	5
valid_sources[0x65]	1528	1			T7	4		T8	1		T36	10
valid_sources[0x66]	2422	1			T7	5		T8	20		T36	4
valid_sources[0x67]	2069	1			T8	2		T10	2		T37	11
valid_sources[0x68]	1563	1			T7	2		T8	8		T36	6
valid_sources[0x69]	1539	1			T3	2		T7	5		T8	9
valid_sources[0x6a]	2320	1			T3	2		T7	8		T8	21
valid_sources[0x6b]	1728	1			T10	2		T36	7		T37	50
valid_sources[0x6c]	1559	1			T7	7		T8	12		T36	2
valid_sources[0x6d]	1581	1			T3	4		T7	3		T8	6
valid_sources[0x6e]	1689	1			T3	2		T7	1		T36	2
valid_sources[0x6f]	2497	1			T7	4		T8	4		T36	2
valid_sources[0x70]	1569	1			T3	1		T7	4		T8	14
valid_sources[0x71]	1852	1			T3	1		T7	3		T8	16
valid_sources[0x72]	1439	1			T8	2		T10	3		T36	5
valid_sources[0x73]	1643	1			T7	5		T8	16		T36	5
valid_sources[0x74]	1468	1			T7	4		T8	11		T36	3
valid_sources[0x75]	1490	1			T3	1		T7	7		T8	13
valid_sources[0x76]	1532	1			T8	3		T10	1		T36	2
valid_sources[0x77]	1648	1			T7	7		T10	1		T36	1
valid_sources[0x78]	1482	1			T7	1		T8	9		T35	2
valid_sources[0x79]	1651	1			T3	6		T8	7		T10	1
valid_sources[0x7a]	1659	1			T35	1		T36	6		T38	5
valid_sources[0x7b]	1758	1			T3	1		T7	3		T8	5
valid_sources[0x7c]	1449	1			T7	9		T10	1		T35	4
valid_sources[0x7d]	2303	1			T7	6		T8	2		T36	2
valid_sources[0x7e]	2188	1			T7	5		T8	6		T37	18
valid_sources[0x7f]	1503	1			T7	2		T8	14		T14	5
valid_sources[0x80]	2961	1			T7	7		T8	18		T39	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73180

1

T1

28

T2

13

T3

30

values[0x0]

all_enables

biggest_size

44552

1

T1

27

T2

12

T3

1

values[0x1]

all_enables

biggest_size

25295

1

T1

13

T2

2

T3

2