Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	18022307	16491	0	0
intr_enable_rd_A	18022307	26485	0	0
reset_en_rd_A	18022307	1446	0	0
reset_en_regwen_rd_A	18022307	1179	0	0
wake_info_capture_dis_rd_A	18022307	1167	0	0
wakeup_en_rd_A	18022307	2346	0	0
wakeup_en_regwen_rd_A	18022307	1175	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18022307	16491	0	0
T13	9474	0	0	0
T14	120818	12	0	0
T21	259180	58	0	0
T22	31777	11	0	0
T37	55069	0	0	0
T38	40262	0	0	0
T40	0	11	0	0
T41	1522	0	0	0
T46	0	76	0	0
T74	10615	0	0	0
T75	3780	0	0	0
T76	0	43	0	0
T83	0	2	0	0
T87	7691	0	0	0
T121	0	138	0	0
T122	0	8	0	0
T123	0	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18022307	26485	0	0
T1	5870	61	0	0
T2	1681	0	0	0
T3	2422	0	0	0
T4	2013	26	0	0
T5	2106	0	0	0
T6	1095	0	0	0
T7	57356	199	0	0
T8	89271	0	0	0
T9	58032	0	0	0
T10	2583	0	0	0
T14	0	836	0	0
T40	0	891	0	0
T45	0	10	0	0
T75	0	29	0	0
T80	0	108	0	0
T124	0	14	0	0
T125	0	25	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18022307	1446	0	0
T13	9474	0	0	0
T14	120818	8	0	0
T21	259180	0	0	0
T22	31777	0	0	0
T29	0	14	0	0
T37	55069	0	0	0
T38	40262	0	0	0
T40	0	19	0	0
T41	1522	0	0	0
T69	0	6	0	0
T74	10615	0	0	0
T75	3780	0	0	0
T79	0	8	0	0
T85	0	17	0	0
T86	0	5	0	0
T87	7691	0	0	0
T126	0	7	0	0
T127	0	9	0	0
T128	0	18	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18022307	1179	0	0
T13	9474	0	0	0
T14	120818	20	0	0
T21	259180	0	0	0
T22	31777	0	0	0
T29	0	11	0	0
T37	55069	0	0	0
T38	40262	0	0	0
T40	0	11	0	0
T41	1522	0	0	0
T74	10615	0	0	0
T75	3780	0	0	0
T79	0	28	0	0
T85	0	18	0	0
T86	0	15	0	0
T87	7691	0	0	0
T123	0	6	0	0
T126	0	11	0	0
T127	0	7	0	0
T129	0	18	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18022307	1167	0	0
T13	9474	0	0	0
T14	120818	12	0	0
T21	259180	0	0	0
T22	31777	0	0	0
T29	0	16	0	0
T37	55069	0	0	0
T38	40262	0	0	0
T40	0	4	0	0
T41	1522	0	0	0
T69	0	8	0	0
T74	10615	0	0	0
T75	3780	0	0	0
T79	0	10	0	0
T85	0	3	0	0
T86	0	2	0	0
T87	7691	0	0	0
T126	0	19	0	0
T127	0	1	0	0
T128	0	16	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18022307	2346	0	0
T13	9474	0	0	0
T14	120818	6	0	0
T21	259180	0	0	0
T22	31777	0	0	0
T29	0	11	0	0
T37	55069	0	0	0
T38	40262	0	0	0
T40	0	21	0	0
T41	1522	0	0	0
T69	0	6	0	0
T74	10615	0	0	0
T75	3780	0	0	0
T79	0	24	0	0
T85	0	7	0	0
T86	0	2	0	0
T87	7691	0	0	0
T126	0	17	0	0
T127	0	15	0	0
T129	0	5	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18022307	1175	0	0
T13	9474	0	0	0
T14	120818	8	0	0
T21	259180	0	0	0
T22	31777	0	0	0
T29	0	8	0	0
T37	55069	0	0	0
T38	40262	0	0	0
T40	0	5	0	0
T41	1522	0	0	0
T74	10615	0	0	0
T75	3780	0	0	0
T79	0	31	0	0
T85	0	9	0	0
T86	0	9	0	0
T87	7691	0	0	0
T123	0	9	0	0
T126	0	16	0	0
T127	0	13	0	0
T129	0	7	0	0