Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	52170951	98018	0	0
StatusRise_A	52170951	110174	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52170951	98018	0	0
T1	17610	47	0	0
T2	5043	3	0	0
T3	7266	6	0	0
T4	6039	15	0	0
T5	6318	12	0	0
T6	3285	12	0	0
T7	172068	213	0	0
T8	267813	461	0	0
T9	174096	224	0	0
T10	7749	54	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52170951	110174	0	0
T1	17610	49	0	0
T2	5043	6	0	0
T3	7266	9	0	0
T4	6039	21	0	0
T5	6318	15	0	0
T6	3285	14	0	0
T7	172068	215	0	0
T8	267813	509	0	0
T9	174096	230	0	0
T10	7749	60	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17390317	36536	0	0
StatusRise_A	17390317	40897	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	36536	0	0
T1	5870	19	0	0
T2	1681	1	0	0
T3	2422	2	0	0
T4	2013	5	0	0
T5	2106	4	0	0
T6	1095	4	0	0
T7	57356	86	0	0
T8	89271	167	0	0
T9	58032	88	0	0
T10	2583	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	40897	0	0
T1	5870	20	0	0
T2	1681	2	0	0
T3	2422	3	0	0
T4	2013	7	0	0
T5	2106	5	0	0
T6	1095	5	0	0
T7	57356	87	0	0
T8	89271	183	0	0
T9	58032	90	0	0
T10	2583	20	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17390317	36535	0	0
StatusRise_A	17390317	40897	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	36535	0	0
T1	5870	19	0	0
T2	1681	1	0	0
T3	2422	2	0	0
T4	2013	5	0	0
T5	2106	4	0	0
T6	1095	4	0	0
T7	57356	86	0	0
T8	89271	167	0	0
T9	58032	88	0	0
T10	2583	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	40897	0	0
T1	5870	20	0	0
T2	1681	2	0	0
T3	2422	3	0	0
T4	2013	7	0	0
T5	2106	5	0	0
T6	1095	5	0	0
T7	57356	87	0	0
T8	89271	183	0	0
T9	58032	90	0	0
T10	2583	20	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17390317	24947	0	0
StatusRise_A	17390317	28380	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	24947	0	0
T1	5870	9	0	0
T2	1681	1	0	0
T3	2422	2	0	0
T4	2013	5	0	0
T5	2106	4	0	0
T6	1095	4	0	0
T7	57356	41	0	0
T8	89271	127	0	0
T9	58032	48	0	0
T10	2583	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	28380	0	0
T1	5870	9	0	0
T2	1681	2	0	0
T3	2422	3	0	0
T4	2013	7	0	0
T5	2106	5	0	0
T6	1095	4	0	0
T7	57356	41	0	0
T8	89271	143	0	0
T9	58032	50	0	0
T10	2583	20	0	0