Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	17390912	9635	0	0
EscTimeoutStoppedByClReset_A	17390317	2483247	0	0
EscTimeoutTriggersReset_A	3276901	466	0	0
RomAllowActiveState_A	17390317	40451	0	0
RomAllowCheckGoodState_A	17390317	40502	0	0
RomBlockActiveState_A	17390317	30057	0	0
RomBlockCheckGoodState_A	17390317	405558	0	0
RomIntgChkDisFalse_A	17390317	16803481	0	0
RomIntgChkDisTrue_A	17390317	197010	0	0
RstreqChkEsctimeout_A	17390317	2864	0	0
RstreqChkFsmterm_A	17390317	160	0	0
RstreqChkGlbesc_A	17390317	2864	0	0
RstreqChkMainpd_A	17390317	827540	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390912	9635	0	0
T11	9794	93	0	0
T12	2421	22	0	0
T13	9475	81	0	0
T14	120819	0	0	0
T35	2520	0	0	0
T36	56886	0	0	0
T37	55069	0	0	0
T38	40263	0	0	0
T39	3117	0	0	0
T41	1522	0	0	0
T131	0	20	0	0
T132	0	2	0	0
T133	0	311	0	0
T134	0	514	0	0
T135	0	26	0	0
T136	0	89	0	0
T137	0	64	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	2483247	0	0
T1	5870	496	0	0
T2	1681	14	0	0
T3	2422	26	0	0
T4	2013	95	0	0
T5	2106	68	0	0
T6	1095	3	0	0
T7	57356	7862	0	0
T8	89271	16102	0	0
T9	58032	10357	0	0
T10	2583	447	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3276901	466	0	0
T11	301	4	0	0
T12	203	2	0	0
T13	440	5	0	0
T14	41636	0	0	0
T35	2177	0	0	0
T36	5795	0	0	0
T37	10507	0	0	0
T38	3827	0	0	0
T39	630	0	0	0
T41	544	0	0	0
T131	0	4	0	0
T132	0	4	0	0
T133	0	4	0	0
T134	0	6	0	0
T135	0	2	0	0
T136	0	5	0	0
T138	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	40451	0	0
T1	5870	20	0	0
T2	1681	2	0	0
T3	2422	3	0	0
T4	2013	7	0	0
T5	2106	5	0	0
T6	1095	5	0	0
T7	57356	87	0	0
T8	89271	183	0	0
T9	58032	90	0	0
T10	2583	20	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	40502	0	0
T1	5870	20	0	0
T2	1681	2	0	0
T3	2422	3	0	0
T4	2013	7	0	0
T5	2106	5	0	0
T6	1095	5	0	0
T7	57356	87	0	0
T8	89271	183	0	0
T9	58032	90	0	0
T10	2583	20	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	30057	0	0
T4	2013	224	0	0
T5	2106	0	0	0
T6	1095	0	0	0
T7	57356	0	0	0
T8	89271	0	0	0
T9	58032	0	0	0
T10	2583	0	0	0
T11	9793	0	0	0
T23	0	795	0	0
T35	2520	0	0	0
T39	3117	0	0	0
T45	0	798	0	0
T125	0	362	0	0
T139	0	236	0	0
T140	0	870	0	0
T141	0	1475	0	0
T142	0	924	0	0
T143	0	1105	0	0
T144	0	824	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	405558	0	0
T4	2013	122	0	0
T5	2106	0	0	0
T6	1095	0	0	0
T7	57356	3986	0	0
T8	89271	756	0	0
T9	58032	3975	0	0
T10	2583	0	0	0
T11	9793	0	0	0
T14	0	507	0	0
T21	0	943	0	0
T35	2520	0	0	0
T36	0	3911	0	0
T37	0	206	0	0
T39	3117	0	0	0
T74	0	184	0	0
T87	0	275	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	16803481	0	0
T1	5870	5773	0	0
T2	1681	1619	0	0
T3	2422	2347	0	0
T4	2013	1748	0	0
T5	2106	1758	0	0
T6	1095	1016	0	0
T7	57356	55942	0	0
T8	89271	88040	0	0
T9	58032	57874	0	0
T10	2583	2469	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	197010	0	0
T4	2013	107	0	0
T5	2106	0	0	0
T6	1095	0	0	0
T7	57356	1347	0	0
T8	89271	0	0	0
T9	58032	0	0	0
T10	2583	0	0	0
T11	9793	0	0	0
T23	0	230	0	0
T35	2520	0	0	0
T39	3117	0	0	0
T45	0	437	0	0
T125	0	1097	0	0
T139	0	900	0	0
T141	0	307	0	0
T142	0	492	0	0
T145	0	1774	0	0
T146	0	467	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	2864	0	0
T4	2013	4	0	0
T5	2106	0	0	0
T6	1095	0	0	0
T7	57356	0	0	0
T8	89271	18	0	0
T9	58032	0	0	0
T10	2583	12	0	0
T11	9793	2	0	0
T12	0	1	0	0
T13	0	2	0	0
T14	0	36	0	0
T35	2520	4	0	0
T37	0	16	0	0
T38	0	12	0	0
T39	3117	0	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	160	0	0
T18	46689	40	0	0
T19	0	20	0	0
T20	0	20	0	0
T24	0	40	0	0
T25	0	40	0	0
T26	976	0	0	0
T27	2329	0	0	0
T28	1672	0	0	0
T29	97874	0	0	0
T30	2126	0	0	0
T31	48324	0	0	0
T32	25810	0	0	0
T33	5203	0	0	0
T34	1180	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	2864	0	0
T4	2013	4	0	0
T5	2106	0	0	0
T6	1095	0	0	0
T7	57356	0	0	0
T8	89271	18	0	0
T9	58032	0	0	0
T10	2583	12	0	0
T11	9793	2	0	0
T12	0	1	0	0
T13	0	2	0	0
T14	0	36	0	0
T35	2520	4	0	0
T37	0	16	0	0
T38	0	12	0	0
T39	3117	0	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17390317	827540	0	0
T4	2013	47	0	0
T5	2106	0	0	0
T6	1095	0	0	0
T7	57356	6745	0	0
T8	89271	6807	0	0
T9	58032	7928	0	0
T10	2583	291	0	0
T11	9793	0	0	0
T14	0	1735	0	0
T35	2520	41	0	0
T36	0	4592	0	0
T37	0	1452	0	0
T38	0	1099	0	0
T39	3117	0	0	0