Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	372553	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

143275

1

T2

1

T3

21

T4

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	266712	1			T1	1		T2	1		T3	25
values[0x0]	124628	1			T3	17		T4	7		T6	10
values[0x1]	124488	1			T3	31		T4	3		T6	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	294648	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

221180

1

T1

1

T2

1

T3

36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2593	1			T7	5		T10	1		T11	7
valid_sources[0x01]	1876	1			T7	4		T8	10		T10	3
valid_sources[0x02]	1656	1			T6	1		T7	2		T8	1
valid_sources[0x03]	1505	1			T7	7		T10	1		T11	14
valid_sources[0x04]	1579	1			T6	1		T10	4		T11	9
valid_sources[0x05]	1788	1			T7	4		T10	4		T11	9
valid_sources[0x06]	1872	1			T7	2		T10	4		T11	24
valid_sources[0x07]	1783	1			T7	3		T10	8		T11	54
valid_sources[0x08]	1542	1			T6	1		T7	1		T10	4
valid_sources[0x09]	1848	1			T8	9		T10	3		T11	14
valid_sources[0x0a]	2937	1			T7	1		T8	5		T10	4
valid_sources[0x0b]	1739	1			T7	5		T10	6		T11	5
valid_sources[0x0c]	2270	1			T7	10		T10	3		T12	10
valid_sources[0x0d]	1937	1			T7	3		T8	1		T11	6
valid_sources[0x0e]	2236	1			T7	3		T10	1		T25	1
valid_sources[0x0f]	1571	1			T6	2		T7	6		T8	1
valid_sources[0x10]	1635	1			T7	3		T10	8		T24	8
valid_sources[0x11]	3698	1			T8	3		T10	4		T11	13
valid_sources[0x12]	1567	1			T7	5		T8	1		T10	3
valid_sources[0x13]	1607	1			T7	2		T10	4		T11	1
valid_sources[0x14]	2036	1			T7	1		T10	6		T11	7
valid_sources[0x15]	1717	1			T7	1		T8	2		T10	6
valid_sources[0x16]	1702	1			T7	5		T8	4		T11	18
valid_sources[0x17]	1882	1			T7	7		T10	4		T11	5
valid_sources[0x18]	1744	1			T7	1		T10	4		T11	17
valid_sources[0x19]	1617	1			T7	4		T10	2		T11	21
valid_sources[0x1a]	1702	1			T7	2		T11	13		T12	19
valid_sources[0x1b]	2112	1			T3	12		T7	3		T8	1
valid_sources[0x1c]	1555	1			T7	1		T10	2		T12	19
valid_sources[0x1d]	1776	1			T7	2		T10	3		T11	9
valid_sources[0x1e]	1706	1			T7	6		T10	7		T11	6
valid_sources[0x1f]	1618	1			T7	1		T10	1		T25	2
valid_sources[0x20]	1571	1			T7	5		T11	44		T12	15
valid_sources[0x21]	2789	1			T7	1		T10	7		T25	4
valid_sources[0x22]	1614	1			T6	1		T7	4		T10	4
valid_sources[0x23]	1848	1			T7	7		T8	2		T10	5
valid_sources[0x24]	1859	1			T10	2		T11	19		T12	16
valid_sources[0x25]	1528	1			T7	7		T10	2		T11	19
valid_sources[0x26]	1444	1			T7	3		T11	11		T12	19
valid_sources[0x27]	2081	1			T7	6		T8	3		T10	5
valid_sources[0x28]	1476	1			T6	1		T7	1		T10	9
valid_sources[0x29]	1894	1			T7	4		T8	3		T10	1
valid_sources[0x2a]	1437	1			T7	5		T8	11		T10	5
valid_sources[0x2b]	1710	1			T7	3		T8	1		T10	4
valid_sources[0x2c]	2083	1			T7	1		T8	2		T10	5
valid_sources[0x2d]	2033	1			T7	4		T10	6		T11	33
valid_sources[0x2e]	1524	1			T7	4		T10	1		T11	14
valid_sources[0x2f]	1960	1			T7	9		T8	2		T10	1
valid_sources[0x30]	1771	1			T10	3		T11	5		T12	14
valid_sources[0x31]	1811	1			T7	1		T8	2		T10	7
valid_sources[0x32]	1793	1			T7	6		T10	4		T11	5
valid_sources[0x33]	2079	1			T7	3		T10	4		T11	37
valid_sources[0x34]	1867	1			T7	3		T10	6		T11	3
valid_sources[0x35]	1939	1			T7	3		T10	4		T11	1
valid_sources[0x36]	1408	1			T7	2		T10	2		T12	19
valid_sources[0x37]	2049	1			T6	1		T7	3		T8	1
valid_sources[0x38]	1964	1			T10	9		T25	21		T11	18
valid_sources[0x39]	1840	1			T7	10		T8	1		T10	5
valid_sources[0x3a]	1899	1			T7	2		T8	7		T10	3
valid_sources[0x3b]	1524	1			T7	2		T10	1		T25	15
valid_sources[0x3c]	2449	1			T7	2		T8	8		T10	6
valid_sources[0x3d]	2117	1			T7	8		T10	1		T11	17
valid_sources[0x3e]	1461	1			T7	2		T10	1		T25	15
valid_sources[0x3f]	2661	1			T7	9		T10	4		T25	16
valid_sources[0x40]	2246	1			T7	3		T10	1		T25	3
valid_sources[0x41]	1611	1			T7	3		T10	6		T11	35
valid_sources[0x42]	1712	1			T6	1		T8	1		T10	3
valid_sources[0x43]	2560	1			T7	8		T10	15		T11	12
valid_sources[0x44]	2405	1			T7	7		T10	2		T11	5
valid_sources[0x45]	2603	1			T7	1		T8	6		T10	2
valid_sources[0x46]	2115	1			T7	4		T10	6		T11	6
valid_sources[0x47]	1962	1			T8	1		T10	3		T11	12
valid_sources[0x48]	1649	1			T7	1		T10	4		T12	15
valid_sources[0x49]	1726	1			T10	2		T11	8		T12	23
valid_sources[0x4a]	1380	1			T10	4		T11	11		T12	11
valid_sources[0x4b]	1976	1			T10	1		T11	10		T12	14
valid_sources[0x4c]	2206	1			T7	3		T8	5		T10	1
valid_sources[0x4d]	2893	1			T3	12		T7	3		T8	1
valid_sources[0x4e]	1561	1			T8	11		T10	2		T11	3
valid_sources[0x4f]	2462	1			T7	2		T10	2		T11	5
valid_sources[0x50]	1718	1			T7	3		T11	20		T12	17
valid_sources[0x51]	1607	1			T10	1		T11	6		T12	19
valid_sources[0x52]	1571	1			T7	1		T10	4		T11	11
valid_sources[0x53]	1801	1			T7	2		T10	1		T11	1
valid_sources[0x54]	1668	1			T7	4		T10	3		T24	3
valid_sources[0x55]	2168	1			T7	5		T10	5		T11	7
valid_sources[0x56]	2517	1			T7	8		T10	6		T11	26
valid_sources[0x57]	2872	1			T7	1		T10	1		T11	5
valid_sources[0x58]	1773	1			T7	2		T9	1		T10	1
valid_sources[0x59]	2369	1			T7	5		T10	2		T25	9
valid_sources[0x5a]	1623	1			T7	4		T10	3		T25	5
valid_sources[0x5b]	1728	1			T7	10		T8	7		T10	3
valid_sources[0x5c]	2480	1			T7	4		T10	7		T25	16
valid_sources[0x5d]	2778	1			T7	1		T8	1		T10	5
valid_sources[0x5e]	2208	1			T7	4		T9	1		T10	2
valid_sources[0x5f]	1515	1			T7	5		T10	1		T11	11
valid_sources[0x60]	2202	1			T7	7		T10	2		T25	55
valid_sources[0x61]	2259	1			T7	6		T8	1		T10	2
valid_sources[0x62]	1589	1			T7	6		T10	4		T11	5
valid_sources[0x63]	2050	1			T7	2		T9	1		T10	1
valid_sources[0x64]	1782	1			T7	2		T10	15		T11	15
valid_sources[0x65]	1871	1			T7	2		T10	1		T25	61
valid_sources[0x66]	2084	1			T7	12		T8	6		T10	4
valid_sources[0x67]	1932	1			T8	7		T10	3		T11	26
valid_sources[0x68]	1621	1			T6	1		T7	2		T10	7
valid_sources[0x69]	1679	1			T7	3		T10	6		T25	5
valid_sources[0x6a]	2710	1			T7	3		T10	3		T11	16
valid_sources[0x6b]	4041	1			T10	5		T11	24		T12	9
valid_sources[0x6c]	2119	1			T8	1		T10	2		T11	10
valid_sources[0x6d]	1929	1			T7	11		T11	6		T12	13
valid_sources[0x6e]	1446	1			T7	3		T8	2		T11	2
valid_sources[0x6f]	1559	1			T7	7		T10	1		T11	18
valid_sources[0x70]	1780	1			T7	7		T10	3		T11	7
valid_sources[0x71]	1857	1			T7	3		T8	3		T10	1
valid_sources[0x72]	1521	1			T7	3		T10	4		T11	2
valid_sources[0x73]	1726	1			T10	2		T11	7		T12	11
valid_sources[0x74]	1651	1			T7	3		T10	3		T25	16
valid_sources[0x75]	2934	1			T7	1		T8	3		T10	1
valid_sources[0x76]	1694	1			T7	2		T8	4		T10	2
valid_sources[0x77]	1692	1			T6	1		T7	3		T10	2
valid_sources[0x78]	2265	1			T7	7		T10	2		T11	7
valid_sources[0x79]	1805	1			T7	2		T9	2		T10	1
valid_sources[0x7a]	2183	1			T7	6		T8	3		T10	2
valid_sources[0x7b]	1598	1			T7	3		T9	1		T10	1
valid_sources[0x7c]	2082	1			T7	1		T10	4		T11	2
valid_sources[0x7d]	3010	1			T7	8		T10	6		T11	13
valid_sources[0x7e]	1797	1			T7	5		T10	1		T11	2
valid_sources[0x7f]	1736	1			T7	4		T8	3		T10	4
valid_sources[0x80]	2663	1			T7	1		T11	18		T12	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70234

1

T2

1

T3

7

T4

10

values[0x0]

all_enables

biggest_size

46867

1

T3

6

T4

4

T6

1

values[0x1]

all_enables

biggest_size

26174

1

T3

8

T6

1

T7

36