Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T10

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	16800034	5071	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	16800034	206863	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	16800034	6854553	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	16800034	206861	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	16800034	5071	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	16800034	206863	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	16800034	6854553	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	16800034	206861	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	5071	0	0
T4	2622	1	0	0
T5	903	0	0	0
T6	2113	2	0	0
T7	62088	24	0	0
T8	10562	8	0	0
T9	10274	0	0	0
T10	59747	24	0	0
T11	147546	36	0	0
T12	0	32	0	0
T18	0	35	0	0
T24	1802	0	0	0
T25	45300	8	0	0
T29	0	41	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	206863	0	0
T4	2622	10	0	0
T5	903	0	0	0
T6	2113	214	0	0
T7	62088	1427	0	0
T8	10562	320	0	0
T9	10274	0	0	0
T10	59747	1520	0	0
T11	147546	1590	0	0
T12	0	1500	0	0
T18	0	1412	0	0
T24	1802	0	0	0
T25	45300	522	0	0
T29	0	2691	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	6854553	0	0
T3	1442	232	0	0
T4	2622	1727	0	0
T5	903	0	0	0
T6	2113	218	0	0
T7	62088	30474	0	0
T8	10562	4408	0	0
T9	10274	0	0	0
T10	59747	31206	0	0
T11	0	71362	0	0
T24	1802	769	0	0
T25	45300	27364	0	0
T26	0	1924	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	206861	0	0
T4	2622	10	0	0
T5	903	0	0	0
T6	2113	214	0	0
T7	62088	1427	0	0
T8	10562	320	0	0
T9	10274	0	0	0
T10	59747	1520	0	0
T11	147546	1601	0	0
T12	0	1500	0	0
T18	0	1412	0	0
T24	1802	0	0	0
T25	45300	522	0	0
T29	0	2691	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	5071	0	0
T4	2622	1	0	0
T5	903	0	0	0
T6	2113	2	0	0
T7	62088	24	0	0
T8	10562	8	0	0
T9	10274	0	0	0
T10	59747	24	0	0
T11	147546	36	0	0
T12	0	32	0	0
T18	0	35	0	0
T24	1802	0	0	0
T25	45300	8	0	0
T29	0	41	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	206863	0	0
T4	2622	10	0	0
T5	903	0	0	0
T6	2113	214	0	0
T7	62088	1427	0	0
T8	10562	320	0	0
T9	10274	0	0	0
T10	59747	1520	0	0
T11	147546	1590	0	0
T12	0	1500	0	0
T18	0	1412	0	0
T24	1802	0	0	0
T25	45300	522	0	0
T29	0	2691	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	6854553	0	0
T3	1442	232	0	0
T4	2622	1727	0	0
T5	903	0	0	0
T6	2113	218	0	0
T7	62088	30474	0	0
T8	10562	4408	0	0
T9	10274	0	0	0
T10	59747	31206	0	0
T11	0	71362	0	0
T24	1802	769	0	0
T25	45300	27364	0	0
T26	0	1924	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	206861	0	0
T4	2622	10	0	0
T5	903	0	0	0
T6	2113	214	0	0
T7	62088	1427	0	0
T8	10562	320	0	0
T9	10274	0	0	0
T10	59747	1520	0	0
T11	147546	1601	0	0
T12	0	1500	0	0
T18	0	1412	0	0
T24	1802	0	0	0
T25	45300	522	0	0
T29	0	2691	0	0