Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	17367185	13140	0	0
intr_enable_rd_A	17367185	30773	0	0
reset_en_rd_A	17367185	875	0	0
reset_en_regwen_rd_A	17367185	780	0	0
wake_info_capture_dis_rd_A	17367185	798	0	0
wakeup_en_rd_A	17367185	1525	0	0
wakeup_en_regwen_rd_A	17367185	784	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17367185	13140	0	0
T11	147546	10	0	0
T12	129508	10	0	0
T18	111430	32	0	0
T26	3030	0	0	0
T27	1700	0	0	0
T28	2944	0	0	0
T29	166065	92	0	0
T30	34862	0	0	0
T31	2482	0	0	0
T32	61674	0	0	0
T33	0	66	0	0
T73	0	66	0	0
T83	0	9	0	0
T116	0	76	0	0
T117	0	17	0	0
T118	0	47	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17367185	30773	0	0
T3	1442	26	0	0
T4	2622	5	0	0
T5	903	0	0	0
T6	2113	0	0	0
T7	62088	166	0	0
T8	10562	0	0	0
T9	10274	0	0	0
T10	59747	142	0	0
T11	0	958	0	0
T19	0	22	0	0
T20	0	24	0	0
T24	1802	0	0	0
T25	45300	0	0	0
T26	0	14	0	0
T32	0	458	0	0
T71	0	430	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17367185	875	0	0
T11	147546	9	0	0
T12	129508	0	0	0
T18	111430	0	0	0
T26	3030	0	0	0
T27	1700	0	0	0
T28	2944	0	0	0
T29	166065	0	0	0
T30	34862	0	0	0
T31	2482	0	0	0
T32	61674	0	0	0
T77	0	18	0	0
T83	0	8	0	0
T117	0	2	0	0
T118	0	18	0	0
T119	0	4	0	0
T120	0	10	0	0
T121	0	9	0	0
T122	0	15	0	0
T123	0	2	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17367185	780	0	0
T11	147546	13	0	0
T12	129508	0	0	0
T18	111430	0	0	0
T26	3030	0	0	0
T27	1700	0	0	0
T28	2944	0	0	0
T29	166065	0	0	0
T30	34862	0	0	0
T31	2482	0	0	0
T32	61674	0	0	0
T77	0	14	0	0
T83	0	6	0	0
T118	0	6	0	0
T119	0	11	0	0
T120	0	3	0	0
T121	0	11	0	0
T122	0	14	0	0
T123	0	9	0	0
T124	0	10	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17367185	798	0	0
T11	147546	17	0	0
T12	129508	0	0	0
T18	111430	0	0	0
T26	3030	0	0	0
T27	1700	0	0	0
T28	2944	0	0	0
T29	166065	0	0	0
T30	34862	0	0	0
T31	2482	0	0	0
T32	61674	0	0	0
T77	0	24	0	0
T83	0	19	0	0
T117	0	1	0	0
T118	0	27	0	0
T119	0	6	0	0
T120	0	8	0	0
T121	0	19	0	0
T122	0	8	0	0
T123	0	2	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17367185	1525	0	0
T11	147546	10	0	0
T12	129508	0	0	0
T18	111430	0	0	0
T26	3030	0	0	0
T27	1700	0	0	0
T28	2944	0	0	0
T29	166065	0	0	0
T30	34862	0	0	0
T31	2482	0	0	0
T32	61674	0	0	0
T77	0	32	0	0
T83	0	2	0	0
T117	0	3	0	0
T118	0	17	0	0
T119	0	17	0	0
T120	0	2	0	0
T121	0	9	0	0
T122	0	9	0	0
T123	0	1	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17367185	784	0	0
T11	147546	3	0	0
T12	129508	0	0	0
T18	111430	0	0	0
T26	3030	0	0	0
T27	1700	0	0	0
T28	2944	0	0	0
T29	166065	0	0	0
T30	34862	0	0	0
T31	2482	0	0	0
T32	61674	0	0	0
T77	0	27	0	0
T83	0	9	0	0
T117	0	8	0	0
T118	0	35	0	0
T119	0	16	0	0
T120	0	12	0	0
T121	0	17	0	0
T122	0	22	0	0
T123	0	1	0	0