Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	50400102	105390	0	0
StatusRise_A	50400102	118402	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400102	105390	0	0
T1	6264	3	0	0
T2	28761	6	0	0
T3	4326	17	0	0
T4	7866	6	0	0
T5	2709	3	0	0
T6	6339	12	0	0
T7	186264	217	0	0
T8	31686	79	0	0
T9	30822	90	0	0
T10	179241	226	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400102	118402	0	0
T1	6264	9	0	0
T2	28761	9	0	0
T3	4326	20	0	0
T4	7866	9	0	0
T5	2709	9	0	0
T6	6339	15	0	0
T7	186264	222	0	0
T8	31686	85	0	0
T9	30822	153	0	0
T10	179241	232	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16800034	39275	0	0
StatusRise_A	16800034	43932	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	39275	0	0
T1	2088	1	0	0
T2	9587	2	0	0
T3	1442	6	0	0
T4	2622	2	0	0
T5	903	1	0	0
T6	2113	4	0	0
T7	62088	90	0	0
T8	10562	32	0	0
T9	10274	30	0	0
T10	59747	89	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	43932	0	0
T1	2088	3	0	0
T2	9587	3	0	0
T3	1442	7	0	0
T4	2622	3	0	0
T5	903	3	0	0
T6	2113	5	0	0
T7	62088	92	0	0
T8	10562	34	0	0
T9	10274	51	0	0
T10	59747	91	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16800034	39275	0	0
StatusRise_A	16800034	43936	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	39275	0	0
T1	2088	1	0	0
T2	9587	2	0	0
T3	1442	6	0	0
T4	2622	2	0	0
T5	903	1	0	0
T6	2113	4	0	0
T7	62088	90	0	0
T8	10562	32	0	0
T9	10274	30	0	0
T10	59747	89	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	43936	0	0
T1	2088	3	0	0
T2	9587	3	0	0
T3	1442	7	0	0
T4	2622	3	0	0
T5	903	3	0	0
T6	2113	5	0	0
T7	62088	92	0	0
T8	10562	34	0	0
T9	10274	51	0	0
T10	59747	91	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16800034	26840	0	0
StatusRise_A	16800034	30534	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	26840	0	0
T1	2088	1	0	0
T2	9587	2	0	0
T3	1442	5	0	0
T4	2622	2	0	0
T5	903	1	0	0
T6	2113	4	0	0
T7	62088	37	0	0
T8	10562	15	0	0
T9	10274	30	0	0
T10	59747	48	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	30534	0	0
T1	2088	3	0	0
T2	9587	3	0	0
T3	1442	6	0	0
T4	2622	3	0	0
T5	903	3	0	0
T6	2113	5	0	0
T7	62088	38	0	0
T8	10562	17	0	0
T9	10274	51	0	0
T10	59747	50	0	0