Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	16800607	11010	0	0
EscTimeoutStoppedByClReset_A	16800034	2273756	0	0
EscTimeoutTriggersReset_A	3858383	449	0	0
RomAllowActiveState_A	16800034	43524	0	0
RomAllowCheckGoodState_A	16800034	43574	0	0
RomBlockActiveState_A	16800034	33258	0	0
RomBlockCheckGoodState_A	16800034	380387	0	0
RomIntgChkDisFalse_A	16800034	16284950	0	0
RomIntgChkDisTrue_A	16800034	108758	0	0
RstreqChkEsctimeout_A	16800034	3274	0	0
RstreqChkFsmterm_A	16800034	120	0	0
RstreqChkGlbesc_A	16800034	3274	0	0
RstreqChkMainpd_A	16800034	726012	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800607	11010	0	0
T2	9588	62	0	0
T3	1443	0	0	0
T4	2623	0	0	0
T5	903	13	0	0
T6	2114	0	0	0
T7	62089	0	0	0
T8	10563	0	0	0
T9	10275	0	0	0
T10	59747	0	0	0
T24	1802	0	0	0
T78	0	386	0	0
T125	0	476	0	0
T126	0	5	0	0
T127	0	319	0	0
T128	0	8	0	0
T129	0	35	0	0
T130	0	89	0	0
T131	0	223	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	2273756	0	0
T1	2088	27	0	0
T2	9587	28	0	0
T3	1442	0	0	0
T4	2622	10	0	0
T5	903	37	0	0
T6	2113	71	0	0
T7	62088	11105	0	0
T8	10562	2320	0	0
T9	10274	1368	0	0
T10	59747	9852	0	0
T24	0	220	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3858383	449	0	0
T1	210	2	0	0
T2	431	4	0	0
T3	426	0	0	0
T4	228	0	0	0
T5	263	5	0	0
T6	382	0	0	0
T7	6454	0	0	0
T8	2313	0	0	0
T9	3508	0	0	0
T10	6390	0	0	0
T31	0	3	0	0
T78	0	5	0	0
T125	0	6	0	0
T126	0	5	0	0
T127	0	6	0	0
T128	0	3	0	0
T132	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	43524	0	0
T1	2088	3	0	0
T2	9587	3	0	0
T3	1442	7	0	0
T4	2622	3	0	0
T5	903	3	0	0
T6	2113	5	0	0
T7	62088	92	0	0
T8	10562	34	0	0
T9	10274	41	0	0
T10	59747	91	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	43574	0	0
T1	2088	3	0	0
T2	9587	3	0	0
T3	1442	7	0	0
T4	2622	3	0	0
T5	903	3	0	0
T6	2113	5	0	0
T7	62088	92	0	0
T8	10562	34	0	0
T9	10274	41	0	0
T10	59747	91	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	33258	0	0
T19	1981	186	0	0
T20	6388	1232	0	0
T21	0	419	0	0
T36	1610	0	0	0
T38	19242	8	0	0
T48	2358	0	0	0
T71	54596	0	0	0
T80	2949	0	0	0
T81	5095	0	0	0
T111	2035	0	0	0
T125	10480	0	0	0
T133	0	582	0	0
T134	0	4	0	0
T135	0	85	0	0
T136	0	734	0	0
T137	0	4	0	0
T138	0	67	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	380387	0	0
T7	62088	4126	0	0
T8	10562	390	0	0
T9	10274	0	0	0
T10	59747	3914	0	0
T11	147546	1057	0	0
T12	129508	1564	0	0
T18	111430	1125	0	0
T24	1802	0	0	0
T25	45300	138	0	0
T26	3030	0	0	0
T29	0	1372	0	0
T30	0	2235	0	0
T33	0	1391	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	16284950	0	0
T1	2088	1920	0	0
T2	9587	9498	0	0
T3	1442	1369	0	0
T4	2622	2523	0	0
T5	903	754	0	0
T6	2113	1772	0	0
T7	62088	61923	0	0
T8	10562	10403	0	0
T9	10274	7195	0	0
T10	59747	59586	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	108758	0	0
T19	1981	97	0	0
T20	6388	1199	0	0
T21	0	1142	0	0
T36	1610	0	0	0
T38	19242	0	0	0
T48	2358	0	0	0
T71	54596	0	0	0
T80	2949	0	0	0
T81	5095	0	0	0
T111	2035	0	0	0
T125	10480	0	0	0
T135	0	82	0	0
T136	0	172	0	0
T138	0	41	0	0
T139	0	1481	0	0
T140	0	1510	0	0
T141	0	14474	0	0
T142	0	1	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	3274	0	0
T1	2088	1	0	0
T2	9587	2	0	0
T3	1442	0	0	0
T4	2622	0	0	0
T5	903	1	0	0
T6	2113	0	0	0
T7	62088	0	0	0
T8	10562	0	0	0
T9	10274	10	0	0
T10	59747	0	0	0
T11	0	19	0	0
T12	0	17	0	0
T18	0	44	0	0
T27	0	1	0	0
T28	0	7	0	0
T29	0	15	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	120	0	0
T9	10274	20	0	0
T10	59747	0	0	0
T11	147546	0	0	0
T12	129508	0	0	0
T16	0	40	0	0
T17	0	20	0	0
T18	111430	0	0	0
T22	0	20	0	0
T23	0	20	0	0
T24	1802	0	0	0
T25	45300	0	0	0
T26	3030	0	0	0
T27	1700	0	0	0
T28	2944	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	3274	0	0
T1	2088	1	0	0
T2	9587	2	0	0
T3	1442	0	0	0
T4	2622	0	0	0
T5	903	1	0	0
T6	2113	0	0	0
T7	62088	0	0	0
T8	10562	0	0	0
T9	10274	10	0	0
T10	59747	0	0	0
T11	0	19	0	0
T12	0	17	0	0
T18	0	44	0	0
T27	0	1	0	0
T28	0	7	0	0
T29	0	15	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16800034	726012	0	0
T7	62088	4958	0	0
T8	10562	1250	0	0
T9	10274	0	0	0
T10	59747	5749	0	0
T11	147546	3983	0	0
T12	129508	4774	0	0
T18	111430	6501	0	0
T24	1802	0	0	0
T25	45300	516	0	0
T26	3030	0	0	0
T28	0	125	0	0
T29	0	8185	0	0
T30	0	1834	0	0