Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	358350	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

143254

1

T1

16

T2

33

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	262520	1			T1	36		T2	182		T3	53
values[0x0]	119248	1			T1	8		T2	31		T3	25
values[0x1]	119836	1			T1	14		T2	31		T3	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	283740	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

217864

1

T1

28

T2

97

T3

34

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1692	1			T1	2		T8	3		T14	12
valid_sources[0x01]	2035	1			T2	3		T8	1		T73	2
valid_sources[0x02]	1550	1			T2	1		T4	1		T8	3
valid_sources[0x03]	1626	1			T1	1		T2	4		T3	1
valid_sources[0x04]	1848	1			T2	4		T8	2		T73	3
valid_sources[0x05]	2147	1			T8	2		T14	9		T21	8
valid_sources[0x06]	1580	1			T2	2		T8	1		T73	3
valid_sources[0x07]	3453	1			T6	1		T20	1		T14	10
valid_sources[0x08]	2501	1			T3	1		T8	2		T20	2
valid_sources[0x09]	2520	1			T2	1		T8	1		T20	1
valid_sources[0x0a]	1668	1			T8	1		T14	5		T36	3
valid_sources[0x0b]	2060	1			T2	2		T3	1		T73	4
valid_sources[0x0c]	1598	1			T2	4		T5	1		T6	1
valid_sources[0x0d]	1537	1			T8	2		T20	2		T14	5
valid_sources[0x0e]	1528	1			T2	1		T6	2		T8	2
valid_sources[0x0f]	1620	1			T20	3		T73	1		T14	9
valid_sources[0x10]	1546	1			T8	1		T73	1		T13	4
valid_sources[0x11]	1775	1			T1	1		T8	2		T20	1
valid_sources[0x12]	3353	1			T2	2		T8	1		T20	1
valid_sources[0x13]	1774	1			T8	3		T14	13		T76	1
valid_sources[0x14]	1463	1			T3	1		T8	5		T20	1
valid_sources[0x15]	1890	1			T8	2		T73	5		T14	8
valid_sources[0x16]	3250	1			T8	1		T20	1		T73	1
valid_sources[0x17]	1558	1			T1	5		T3	3		T8	2
valid_sources[0x18]	2379	1			T6	1		T8	2		T20	1
valid_sources[0x19]	1509	1			T8	1		T20	1		T73	1
valid_sources[0x1a]	1990	1			T8	3		T20	1		T73	5
valid_sources[0x1b]	1558	1			T2	1		T8	1		T20	1
valid_sources[0x1c]	1834	1			T8	2		T73	2		T13	5
valid_sources[0x1d]	1883	1			T8	1		T20	1		T13	3
valid_sources[0x1e]	3580	1			T3	2		T8	1		T20	2
valid_sources[0x1f]	1888	1			T20	2		T73	2		T13	1
valid_sources[0x20]	1581	1			T20	3		T13	18		T14	12
valid_sources[0x21]	2638	1			T3	2		T8	3		T20	1
valid_sources[0x22]	1884	1			T3	2		T6	1		T8	1
valid_sources[0x23]	3978	1			T3	1		T8	1		T20	1
valid_sources[0x24]	1830	1			T1	2		T8	1		T20	1
valid_sources[0x25]	1944	1			T6	1		T8	3		T20	1
valid_sources[0x26]	1672	1			T2	1		T3	1		T8	3
valid_sources[0x27]	2267	1			T6	2		T8	3		T20	3
valid_sources[0x28]	2160	1			T20	1		T13	22		T14	16
valid_sources[0x29]	2019	1			T2	10		T8	1		T13	5
valid_sources[0x2a]	1892	1			T3	1		T73	4		T13	1
valid_sources[0x2b]	1557	1			T1	2		T2	4		T3	2
valid_sources[0x2c]	3989	1			T8	1		T13	3		T14	9
valid_sources[0x2d]	2203	1			T3	1		T8	2		T20	1
valid_sources[0x2e]	1645	1			T2	1		T8	2		T14	7
valid_sources[0x2f]	1662	1			T2	5		T3	1		T6	1
valid_sources[0x30]	1789	1			T8	2		T13	21		T14	9
valid_sources[0x31]	1697	1			T13	2		T14	11		T36	1
valid_sources[0x32]	1678	1			T8	3		T13	1		T14	11
valid_sources[0x33]	1570	1			T2	3		T3	1		T8	1
valid_sources[0x34]	1755	1			T3	1		T8	3		T20	1
valid_sources[0x35]	1883	1			T20	2		T73	1		T14	4
valid_sources[0x36]	1721	1			T1	2		T8	1		T20	1
valid_sources[0x37]	1907	1			T2	1		T20	3		T73	3
valid_sources[0x38]	2627	1			T1	3		T3	1		T8	1
valid_sources[0x39]	1645	1			T2	1		T3	1		T73	1
valid_sources[0x3a]	1803	1			T2	1		T3	1		T73	1
valid_sources[0x3b]	1644	1			T8	1		T13	2		T14	12
valid_sources[0x3c]	1628	1			T2	5		T6	1		T8	4
valid_sources[0x3d]	1662	1			T8	3		T13	3		T14	9
valid_sources[0x3e]	1470	1			T8	5		T20	1		T73	3
valid_sources[0x3f]	1808	1			T2	1		T3	2		T8	6
valid_sources[0x40]	2116	1			T73	2		T13	10		T14	6
valid_sources[0x41]	1605	1			T1	1		T8	2		T13	3
valid_sources[0x42]	2502	1			T8	1		T20	1		T13	6
valid_sources[0x43]	1643	1			T3	1		T6	2		T8	1
valid_sources[0x44]	1558	1			T8	2		T20	1		T73	1
valid_sources[0x45]	1760	1			T3	2		T8	1		T20	2
valid_sources[0x46]	2228	1			T20	1		T73	1		T14	12
valid_sources[0x47]	1472	1			T3	1		T8	2		T14	12
valid_sources[0x48]	1981	1			T8	4		T20	1		T14	5
valid_sources[0x49]	1966	1			T2	2		T3	2		T14	6
valid_sources[0x4a]	2717	1			T2	2		T3	1		T8	1
valid_sources[0x4b]	1638	1			T2	4		T8	2		T20	1
valid_sources[0x4c]	1528	1			T2	3		T8	2		T20	2
valid_sources[0x4d]	3480	1			T6	1		T73	3		T14	14
valid_sources[0x4e]	1947	1			T2	1		T8	1		T20	1
valid_sources[0x4f]	1609	1			T3	1		T20	2		T13	9
valid_sources[0x50]	3113	1			T2	2		T6	2		T8	1
valid_sources[0x51]	1838	1			T8	2		T20	2		T73	1
valid_sources[0x52]	2115	1			T2	2		T8	5		T20	1
valid_sources[0x53]	1540	1			T6	1		T8	1		T20	3
valid_sources[0x54]	1676	1			T8	1		T20	1		T14	3
valid_sources[0x55]	1528	1			T2	1		T13	6		T14	18
valid_sources[0x56]	2534	1			T1	1		T8	1		T20	1
valid_sources[0x57]	1549	1			T73	1		T13	18		T14	9
valid_sources[0x58]	2170	1			T73	1		T13	1		T14	8
valid_sources[0x59]	1513	1			T2	3		T6	1		T8	3
valid_sources[0x5a]	1873	1			T1	3		T13	10		T14	5
valid_sources[0x5b]	1593	1			T6	1		T20	2		T73	2
valid_sources[0x5c]	2269	1			T2	7		T20	3		T13	15
valid_sources[0x5d]	1857	1			T2	6		T3	3		T20	1
valid_sources[0x5e]	4679	1			T6	1		T8	4		T20	2
valid_sources[0x5f]	2776	1			T2	7		T3	1		T20	1
valid_sources[0x60]	1489	1			T2	1		T13	22		T14	12
valid_sources[0x61]	1758	1			T6	1		T20	2		T73	1
valid_sources[0x62]	1343	1			T20	1		T73	5		T13	1
valid_sources[0x63]	3142	1			T6	1		T8	3		T20	3
valid_sources[0x64]	3634	1			T20	2		T13	2		T14	12
valid_sources[0x65]	1684	1			T2	1		T8	2		T14	10
valid_sources[0x66]	1604	1			T1	3		T3	1		T8	1
valid_sources[0x67]	1464	1			T2	4		T3	3		T8	1
valid_sources[0x68]	2032	1			T8	1		T20	1		T73	3
valid_sources[0x69]	4255	1			T2	5		T20	1		T14	11
valid_sources[0x6a]	1777	1			T3	1		T20	1		T73	1
valid_sources[0x6b]	1796	1			T2	1		T20	3		T73	1
valid_sources[0x6c]	1689	1			T3	1		T8	3		T20	1
valid_sources[0x6d]	4094	1			T1	3		T20	1		T13	2
valid_sources[0x6e]	1734	1			T1	1		T2	6		T8	2
valid_sources[0x6f]	1523	1			T2	2		T8	1		T20	1
valid_sources[0x70]	1443	1			T8	3		T20	2		T73	2
valid_sources[0x71]	1680	1			T2	5		T8	2		T20	1
valid_sources[0x72]	1956	1			T8	2		T20	2		T73	1
valid_sources[0x73]	1890	1			T8	2		T73	2		T14	4
valid_sources[0x74]	2528	1			T2	11		T8	2		T20	1
valid_sources[0x75]	1605	1			T2	11		T8	5		T13	8
valid_sources[0x76]	1400	1			T6	1		T20	2		T14	10
valid_sources[0x77]	1629	1			T20	2		T73	1		T13	3
valid_sources[0x78]	1552	1			T8	1		T20	3		T13	13
valid_sources[0x79]	1458	1			T8	2		T20	1		T13	10
valid_sources[0x7a]	2162	1			T8	3		T20	2		T13	3
valid_sources[0x7b]	2497	1			T3	1		T73	1		T14	8
valid_sources[0x7c]	1831	1			T8	2		T20	2		T73	1
valid_sources[0x7d]	1882	1			T2	4		T8	3		T20	2
valid_sources[0x7e]	4102	1			T20	2		T73	1		T13	1
valid_sources[0x7f]	2052	1			T6	1		T8	2		T20	2
valid_sources[0x80]	1342	1			T3	2		T8	1		T20	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71320

1

T1

8

T2

16

T3

11

values[0x0]

all_enables

biggest_size

45726

1

T1

3

T2

12

T3

10

values[0x1]

all_enables

biggest_size

26208

1

T1

5

T2

5

T3

2