SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34993 | 1 | T28 | 335 | T31 | 280 | T89 | 300 | ||||
others[1] | 34934 | 1 | T28 | 282 | T31 | 303 | T24 | 1 | ||||
others[2] | 34985 | 1 | T28 | 290 | T31 | 296 | T89 | 268 | ||||
others[3] | 58448 | 1 | T1 | 1 | T28 | 504 | T31 | 532 | ||||
false | 13267 | 1 | T1 | 2 | T6 | 3 | T8 | 40 | ||||
true | 21812 | 1 | T1 | 4 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34784 | 1 | T6 | 1 | T28 | 296 | T31 | 309 | ||||
others[1] | 34875 | 1 | T28 | 320 | T31 | 300 | T89 | 303 | ||||
others[2] | 35189 | 1 | T6 | 1 | T25 | 1 | T38 | 1 | ||||
others[3] | 58730 | 1 | T28 | 516 | T31 | 503 | T89 | 480 | ||||
false | 9239 | 1 | T1 | 3 | T6 | 3 | T8 | 20 | ||||
true | 17841 | 1 | T1 | 4 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 549 | 1 | T2 | 6 | T73 | 4 | T35 | 2 | ||||
others[1] | 538 | 1 | T2 | 6 | T73 | 6 | T12 | 1 | ||||
others[2] | 545 | 1 | T2 | 4 | T73 | 7 | T35 | 1 | ||||
others[3] | 949 | 1 | T2 | 9 | T73 | 8 | T36 | 4 | ||||
false | 10180 | 1 | T1 | 4 | T2 | 4 | T3 | 1 | ||||
true | 2680 | 1 | T1 | 3 | T2 | 1 | T6 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |