Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T41

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	15862163	4651	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	15862163	190839	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	15862163	6340381	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	15862163	190859	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	15862163	4651	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	15862163	190839	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	15862163	6340381	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	15862163	190859	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	4651	0	0
T8	10312	11	0	0
T9	9565	0	0	0
T10	2164	0	0	0
T12	7178	0	0	0
T13	23719	11	0	0
T14	72448	19	0	0
T20	10269	6	0	0
T21	0	20	0	0
T28	0	29	0	0
T36	0	15	0	0
T41	0	3	0	0
T43	0	2	0	0
T73	4103	0	0	0
T74	0	1	0	0
T75	11970	0	0	0
T76	2329	0	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	190839	0	0
T8	10312	270	0	0
T9	9565	0	0	0
T10	2164	0	0	0
T12	7178	0	0	0
T13	23719	303	0	0
T14	72448	676	0	0
T20	10269	211	0	0
T21	0	582	0	0
T28	0	681	0	0
T36	0	424	0	0
T41	0	582	0	0
T43	0	454	0	0
T73	4103	0	0	0
T74	0	13	0	0
T75	11970	0	0	0
T76	2329	0	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	6340381	0	0
T3	2512	674	0	0
T4	1198	0	0	0
T5	2483	0	0	0
T6	1806	0	0	0
T7	1347	511	0	0
T8	10312	6022	0	0
T9	9565	0	0	0
T10	2164	1547	0	0
T13	0	13329	0	0
T14	0	38623	0	0
T20	10269	5583	0	0
T36	0	23190	0	0
T41	0	1165	0	0
T73	4103	0	0	0
T75	0	6198	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	190859	0	0
T8	10312	270	0	0
T9	9565	0	0	0
T10	2164	0	0	0
T12	7178	0	0	0
T13	23719	303	0	0
T14	72448	671	0	0
T20	10269	211	0	0
T21	0	582	0	0
T28	0	681	0	0
T36	0	424	0	0
T41	0	582	0	0
T43	0	454	0	0
T73	4103	0	0	0
T74	0	13	0	0
T75	11970	0	0	0
T76	2329	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	4651	0	0
T8	10312	11	0	0
T9	9565	0	0	0
T10	2164	0	0	0
T12	7178	0	0	0
T13	23719	11	0	0
T14	72448	19	0	0
T20	10269	6	0	0
T21	0	20	0	0
T28	0	29	0	0
T36	0	15	0	0
T41	0	3	0	0
T43	0	2	0	0
T73	4103	0	0	0
T74	0	1	0	0
T75	11970	0	0	0
T76	2329	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	190839	0	0
T8	10312	270	0	0
T9	9565	0	0	0
T10	2164	0	0	0
T12	7178	0	0	0
T13	23719	303	0	0
T14	72448	676	0	0
T20	10269	211	0	0
T21	0	582	0	0
T28	0	681	0	0
T36	0	424	0	0
T41	0	582	0	0
T43	0	454	0	0
T73	4103	0	0	0
T74	0	13	0	0
T75	11970	0	0	0
T76	2329	0	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	6340381	0	0
T3	2512	674	0	0
T4	1198	0	0	0
T5	2483	0	0	0
T6	1806	0	0	0
T7	1347	511	0	0
T8	10312	6022	0	0
T9	9565	0	0	0
T10	2164	1547	0	0
T13	0	13329	0	0
T14	0	38623	0	0
T20	10269	5583	0	0
T36	0	23190	0	0
T41	0	1165	0	0
T73	4103	0	0	0
T75	0	6198	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	190859	0	0
T8	10312	270	0	0
T9	9565	0	0	0
T10	2164	0	0	0
T12	7178	0	0	0
T13	23719	303	0	0
T14	72448	671	0	0
T20	10269	211	0	0
T21	0	582	0	0
T28	0	681	0	0
T36	0	424	0	0
T41	0	582	0	0
T43	0	454	0	0
T73	4103	0	0	0
T74	0	13	0	0
T75	11970	0	0	0
T76	2329	0	0	0