Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	16475483	16411	0	0
intr_enable_rd_A	16475483	28544	0	0
reset_en_rd_A	16475483	1507	0	0
reset_en_regwen_rd_A	16475483	1288	0	0
wake_info_capture_dis_rd_A	16475483	1272	0	0
wakeup_en_rd_A	16475483	2417	0	0
wakeup_en_regwen_rd_A	16475483	1279	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16475483	16411	0	0
T22	58536	31	0	0
T23	119650	30	0	0
T24	179288	189	0	0
T31	18147	0	0	0
T32	1645	0	0	0
T33	850	0	0	0
T34	6200	0	0	0
T56	0	87	0	0
T84	3240	0	0	0
T85	2552	0	0	0
T86	2893	0	0	0
T98	0	77	0	0
T100	0	42	0	0
T128	0	6	0	0
T129	0	1	0	0
T130	0	22	0	0
T131	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16475483	28544	0	0
T6	1806	9	0	0
T7	1347	0	0	0
T8	10312	67	0	0
T9	9565	0	0	0
T10	2164	0	0	0
T12	7178	0	0	0
T13	23719	0	0	0
T14	72448	540	0	0
T20	10269	0	0	0
T25	0	16	0	0
T28	0	174	0	0
T36	0	371	0	0
T38	0	11	0	0
T73	4103	104	0	0
T75	0	12	0	0
T77	0	28	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16475483	1507	0	0
T22	58536	17	0	0
T23	119650	0	0	0
T24	179288	0	0	0
T31	18147	0	0	0
T32	1645	0	0	0
T33	850	0	0	0
T34	6200	0	0	0
T63	0	6	0	0
T79	0	16	0	0
T80	0	11	0	0
T82	0	4	0	0
T84	3240	0	0	0
T85	2552	0	0	0
T86	2893	0	0	0
T92	0	3	0	0
T128	0	15	0	0
T129	0	4	0	0
T132	0	17	0	0
T133	0	3	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16475483	1288	0	0
T22	58536	30	0	0
T23	119650	0	0	0
T24	179288	0	0	0
T31	18147	0	0	0
T32	1645	0	0	0
T33	850	0	0	0
T34	6200	0	0	0
T63	0	16	0	0
T80	0	15	0	0
T82	0	7	0	0
T84	3240	0	0	0
T85	2552	0	0	0
T86	2893	0	0	0
T92	0	4	0	0
T128	0	9	0	0
T129	0	5	0	0
T132	0	12	0	0
T133	0	12	0	0
T134	0	6	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16475483	1272	0	0
T22	58536	5	0	0
T23	119650	0	0	0
T24	179288	0	0	0
T31	18147	0	0	0
T32	1645	0	0	0
T33	850	0	0	0
T34	6200	0	0	0
T63	0	19	0	0
T79	0	7	0	0
T80	0	8	0	0
T84	3240	0	0	0
T85	2552	0	0	0
T86	2893	0	0	0
T128	0	3	0	0
T129	0	1	0	0
T132	0	20	0	0
T133	0	6	0	0
T134	0	11	0	0
T135	0	18	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16475483	2417	0	0
T22	58536	9	0	0
T23	119650	0	0	0
T24	179288	0	0	0
T31	18147	0	0	0
T32	1645	0	0	0
T33	850	0	0	0
T34	6200	0	0	0
T63	0	9	0	0
T79	0	15	0	0
T80	0	8	0	0
T84	3240	0	0	0
T85	2552	0	0	0
T86	2893	0	0	0
T92	0	9	0	0
T128	0	2	0	0
T129	0	4	0	0
T132	0	19	0	0
T133	0	12	0	0
T134	0	13	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16475483	1279	0	0
T22	58536	12	0	0
T23	119650	0	0	0
T24	179288	0	0	0
T31	18147	0	0	0
T32	1645	0	0	0
T33	850	0	0	0
T34	6200	0	0	0
T63	0	18	0	0
T80	0	9	0	0
T82	0	8	0	0
T84	3240	0	0	0
T85	2552	0	0	0
T86	2893	0	0	0
T128	0	9	0	0
T129	0	1	0	0
T132	0	20	0	0
T133	0	15	0	0
T134	0	5	0	0
T135	0	17	0	0