Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	47586489	100419	0	0
StatusRise_A	47586489	112944	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47586489	100419	0	0
T1	9132	27	0	0
T2	9246	3	0	0
T3	7536	16	0	0
T4	3594	0	0	0
T5	7449	3	0	0
T6	5418	15	0	0
T7	4041	3	0	0
T8	30936	95	0	0
T9	28695	6	0	0
T10	6492	10	0	0
T20	0	63	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47586489	112944	0	0
T1	9132	30	0	0
T2	9246	6	0	0
T3	7536	18	0	0
T4	3594	6	0	0
T5	7449	9	0	0
T6	5418	21	0	0
T7	4041	6	0	0
T8	30936	97	0	0
T9	28695	9	0	0
T10	6492	13	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	15862163	37321	0	0
StatusRise_A	15862163	41781	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	37321	0	0
T1	3044	9	0	0
T2	3082	1	0	0
T3	2512	6	0	0
T4	1198	0	0	0
T5	2483	1	0	0
T6	1806	5	0	0
T7	1347	1	0	0
T8	10312	37	0	0
T9	9565	2	0	0
T10	2164	4	0	0
T20	0	25	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	41781	0	0
T1	3044	10	0	0
T2	3082	2	0	0
T3	2512	7	0	0
T4	1198	2	0	0
T5	2483	3	0	0
T6	1806	7	0	0
T7	1347	2	0	0
T8	10312	38	0	0
T9	9565	3	0	0
T10	2164	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	15862163	37320	0	0
StatusRise_A	15862163	41784	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	37320	0	0
T1	3044	9	0	0
T2	3082	1	0	0
T3	2512	6	0	0
T4	1198	0	0	0
T5	2483	1	0	0
T6	1806	5	0	0
T7	1347	1	0	0
T8	10312	37	0	0
T9	9565	2	0	0
T10	2164	4	0	0
T20	0	25	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	41784	0	0
T1	3044	10	0	0
T2	3082	2	0	0
T3	2512	7	0	0
T4	1198	2	0	0
T5	2483	3	0	0
T6	1806	7	0	0
T7	1347	2	0	0
T8	10312	38	0	0
T9	9565	3	0	0
T10	2164	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	15862163	25778	0	0
StatusRise_A	15862163	29379	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	25778	0	0
T1	3044	9	0	0
T2	3082	1	0	0
T3	2512	4	0	0
T4	1198	0	0	0
T5	2483	1	0	0
T6	1806	5	0	0
T7	1347	1	0	0
T8	10312	21	0	0
T9	9565	2	0	0
T10	2164	2	0	0
T20	0	13	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	29379	0	0
T1	3044	10	0	0
T2	3082	2	0	0
T3	2512	4	0	0
T4	1198	2	0	0
T5	2483	3	0	0
T6	1806	7	0	0
T7	1347	2	0	0
T8	10312	21	0	0
T9	9565	3	0	0
T10	2164	3	0	0