Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	15862750	11082	0	0
EscTimeoutStoppedByClReset_A	15862163	2167741	0	0
EscTimeoutTriggersReset_A	3701135	417	0	0
RomAllowActiveState_A	15862163	41370	0	0
RomAllowCheckGoodState_A	15862163	41421	0	0
RomBlockActiveState_A	15862163	28059	0	0
RomBlockCheckGoodState_A	15862163	340730	0	0
RomIntgChkDisFalse_A	15862163	15360733	0	0
RomIntgChkDisTrue_A	15862163	97862	0	0
RstreqChkEsctimeout_A	15862163	3140	0	0
RstreqChkFsmterm_A	15862163	200	0	0
RstreqChkGlbesc_A	15862163	3140	0	0
RstreqChkMainpd_A	15862163	676877	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862750	11082	0	0
T9	9566	89	0	0
T10	2165	0	0	0
T11	0	2	0	0
T12	7178	0	0	0
T13	23720	0	0	0
T14	72449	0	0	0
T20	10269	0	0	0
T33	0	5	0	0
T41	3073	0	0	0
T73	4104	0	0	0
T75	11971	0	0	0
T76	2329	0	0	0
T102	0	115	0	0
T136	0	34	0	0
T137	0	14	0	0
T138	0	50	0	0
T139	0	164	0	0
T140	0	15	0	0
T141	0	3	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	2167741	0	0
T1	3044	273	0	0
T2	3082	11	0	0
T3	2512	358	0	0
T4	1198	20	0	0
T5	2483	25	0	0
T6	1806	178	0	0
T7	1347	0	0	0
T8	10312	1185	0	0
T9	9565	26	0	0
T10	2164	93	0	0
T20	0	1861	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3701135	417	0	0
T5	218	2	0	0
T6	559	0	0	0
T7	120	0	0	0
T8	3616	0	0	0
T9	436	5	0	0
T10	718	0	0	0
T11	0	4	0	0
T13	9540	0	0	0
T14	25390	0	0	0
T20	2023	0	0	0
T33	0	3	0	0
T73	1211	0	0	0
T85	0	2	0	0
T102	0	6	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	4	0	0
T142	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	41370	0	0
T1	3044	10	0	0
T2	3082	2	0	0
T3	2512	7	0	0
T4	1198	2	0	0
T5	2483	3	0	0
T6	1806	7	0	0
T7	1347	2	0	0
T8	10312	38	0	0
T9	9565	3	0	0
T10	2164	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	41421	0	0
T1	3044	10	0	0
T2	3082	2	0	0
T3	2512	7	0	0
T4	1198	2	0	0
T5	2483	3	0	0
T6	1806	7	0	0
T7	1347	2	0	0
T8	10312	38	0	0
T9	9565	3	0	0
T10	2164	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	28059	0	0
T1	3044	358	0	0
T2	3082	0	0	0
T3	2512	0	0	0
T4	1198	0	0	0
T5	2483	0	0	0
T6	1806	74	0	0
T7	1347	0	0	0
T8	10312	0	0	0
T9	9565	0	0	0
T10	2164	0	0	0
T25	0	167	0	0
T38	0	538	0	0
T89	0	7	0	0
T143	0	286	0	0
T144	0	4	0	0
T145	0	8	0	0
T146	0	289	0	0
T147	0	1087	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	340730	0	0
T1	3044	309	0	0
T2	3082	0	0	0
T3	2512	0	0	0
T4	1198	0	0	0
T5	2483	0	0	0
T6	1806	71	0	0
T7	1347	0	0	0
T8	10312	459	0	0
T9	9565	0	0	0
T10	2164	0	0	0
T13	0	436	0	0
T14	0	983	0	0
T20	0	368	0	0
T21	0	755	0	0
T25	0	85	0	0
T36	0	480	0	0
T38	0	652	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	15360733	0	0
T1	3044	2555	0	0
T2	3082	2985	0	0
T3	2512	2461	0	0
T4	1198	1091	0	0
T5	2483	2341	0	0
T6	1806	919	0	0
T7	1347	1248	0	0
T8	10312	10243	0	0
T9	9565	9494	0	0
T10	2164	2095	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	97862	0	0
T1	3044	418	0	0
T2	3082	0	0	0
T3	2512	0	0	0
T4	1198	0	0	0
T5	2483	0	0	0
T6	1806	768	0	0
T7	1347	0	0	0
T8	10312	0	0	0
T9	9565	0	0	0
T10	2164	0	0	0
T25	0	199	0	0
T28	0	426	0	0
T31	0	474	0	0
T38	0	867	0	0
T89	0	498	0	0
T143	0	1102	0	0
T148	0	4530	0	0
T149	0	2940	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	3140	0	0
T1	3044	2	0	0
T2	3082	0	0	0
T3	2512	0	0	0
T4	1198	0	0	0
T5	2483	1	0	0
T6	1806	2	0	0
T7	1347	0	0	0
T8	10312	0	0	0
T9	9565	2	0	0
T10	2164	0	0	0
T11	0	1	0	0
T12	0	6	0	0
T25	0	3	0	0
T35	0	7	0	0
T36	0	24	0	0
T37	0	3	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	200	0	0
T17	17750	40	0	0
T18	0	40	0	0
T19	0	40	0	0
T22	58536	0	0	0
T23	119650	0	0	0
T26	0	40	0	0
T27	0	40	0	0
T28	25366	0	0	0
T29	3394	0	0	0
T30	4115	0	0	0
T31	18147	0	0	0
T32	1645	0	0	0
T33	850	0	0	0
T34	6200	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	3140	0	0
T1	3044	2	0	0
T2	3082	0	0	0
T3	2512	0	0	0
T4	1198	0	0	0
T5	2483	1	0	0
T6	1806	2	0	0
T7	1347	0	0	0
T8	10312	0	0	0
T9	9565	2	0	0
T10	2164	0	0	0
T11	0	1	0	0
T12	0	6	0	0
T25	0	3	0	0
T35	0	7	0	0
T36	0	24	0	0
T37	0	3	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15862163	676877	0	0
T1	3044	868	0	0
T2	3082	0	0	0
T3	2512	0	0	0
T4	1198	5	0	0
T5	2483	0	0	0
T6	1806	97	0	0
T7	1347	0	0	0
T8	10312	808	0	0
T9	9565	0	0	0
T10	2164	0	0	0
T12	0	100	0	0
T13	0	803	0	0
T14	0	1537	0	0
T20	0	748	0	0
T35	0	112	0	0
T36	0	1363	0	0