Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	373319	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

149257

1

T1

28

T2

32

T3

57

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	274356	1			T1	42		T2	103		T3	102
values[0x0]	123732	1			T1	5		T2	32		T3	64
values[0x1]	124488	1			T1	5		T2	34		T3	66

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	295271	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

227305

1

T1

32

T2

70

T3

101

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2164	1			T7	5		T23	1		T15	2
valid_sources[0x01]	1804	1			T2	2		T7	4		T42	1
valid_sources[0x02]	1644	1			T2	1		T6	3		T7	3
valid_sources[0x03]	1716	1			T6	14		T7	3		T8	8
valid_sources[0x04]	1674	1			T2	1		T3	1		T7	5
valid_sources[0x05]	1655	1			T2	2		T6	1		T7	4
valid_sources[0x06]	2989	1			T2	1		T7	2		T38	2
valid_sources[0x07]	1627	1			T2	1		T7	3		T15	2
valid_sources[0x08]	1755	1			T7	6		T8	2		T33	6
valid_sources[0x09]	1922	1			T5	1		T38	2		T31	2
valid_sources[0x0a]	1604	1			T2	3		T3	3		T7	3
valid_sources[0x0b]	2606	1			T2	1		T7	2		T31	2
valid_sources[0x0c]	2914	1			T2	1		T7	7		T32	1
valid_sources[0x0d]	2366	1			T5	1		T15	3		T36	6
valid_sources[0x0e]	1856	1			T2	3		T7	4		T8	1
valid_sources[0x0f]	1827	1			T3	4		T7	4		T8	5
valid_sources[0x10]	1785	1			T7	3		T8	2		T31	2
valid_sources[0x11]	1835	1			T7	1		T8	2		T23	1
valid_sources[0x12]	2002	1			T2	2		T7	1		T15	12
valid_sources[0x13]	1687	1			T2	1		T7	4		T8	1
valid_sources[0x14]	1596	1			T2	1		T7	9		T8	5
valid_sources[0x15]	2135	1			T1	2		T6	20		T7	5
valid_sources[0x16]	1837	1			T7	7		T23	2		T42	2
valid_sources[0x17]	1541	1			T2	1		T7	5		T8	1
valid_sources[0x18]	1974	1			T7	2		T31	1		T15	6
valid_sources[0x19]	1956	1			T2	2		T7	1		T34	1
valid_sources[0x1a]	1759	1			T8	1		T31	1		T15	8
valid_sources[0x1b]	1891	1			T2	1		T7	2		T15	3
valid_sources[0x1c]	1498	1			T7	2		T8	1		T15	2
valid_sources[0x1d]	1800	1			T3	7		T7	1		T31	1
valid_sources[0x1e]	1672	1			T7	3		T8	4		T33	3
valid_sources[0x1f]	1962	1			T3	4		T31	3		T33	4
valid_sources[0x20]	2932	1			T3	7		T6	1		T42	2
valid_sources[0x21]	1798	1			T6	5		T7	5		T8	4
valid_sources[0x22]	2151	1			T2	2		T7	2		T33	3
valid_sources[0x23]	1708	1			T2	1		T8	1		T31	1
valid_sources[0x24]	3922	1			T7	4		T8	4		T31	1
valid_sources[0x25]	1776	1			T2	1		T7	6		T42	2
valid_sources[0x26]	2573	1			T3	2		T31	3		T15	5
valid_sources[0x27]	1596	1			T7	3		T23	1		T34	2
valid_sources[0x28]	2070	1			T7	3		T15	13		T36	2
valid_sources[0x29]	1692	1			T6	3		T7	7		T8	4
valid_sources[0x2a]	1552	1			T7	4		T8	1		T31	1
valid_sources[0x2b]	1673	1			T2	2		T7	4		T31	3
valid_sources[0x2c]	1782	1			T3	12		T7	7		T31	1
valid_sources[0x2d]	1955	1			T2	1		T7	3		T8	2
valid_sources[0x2e]	2187	1			T7	3		T31	1		T34	2
valid_sources[0x2f]	2576	1			T2	1		T3	3		T7	4
valid_sources[0x30]	1740	1			T6	8		T7	7		T31	1
valid_sources[0x31]	1913	1			T2	1		T6	1		T7	2
valid_sources[0x32]	1672	1			T2	1		T7	1		T20	1
valid_sources[0x33]	2165	1			T2	2		T3	5		T7	5
valid_sources[0x34]	2550	1			T7	3		T8	8		T15	2
valid_sources[0x35]	2153	1			T3	5		T7	2		T8	1
valid_sources[0x36]	1744	1			T2	1		T7	4		T8	1
valid_sources[0x37]	1696	1			T2	1		T3	1		T7	4
valid_sources[0x38]	1810	1			T3	2		T7	3		T15	3
valid_sources[0x39]	1822	1			T6	4		T7	7		T31	1
valid_sources[0x3a]	1889	1			T2	3		T7	2		T31	2
valid_sources[0x3b]	1552	1			T2	1		T3	3		T7	2
valid_sources[0x3c]	1525	1			T2	1		T3	2		T7	2
valid_sources[0x3d]	1839	1			T3	6		T6	5		T42	1
valid_sources[0x3e]	2968	1			T2	1		T7	8		T8	1
valid_sources[0x3f]	2045	1			T3	5		T6	6		T7	5
valid_sources[0x40]	3432	1			T7	1		T31	1		T15	11
valid_sources[0x41]	1803	1			T7	8		T8	1		T15	9
valid_sources[0x42]	1784	1			T2	2		T7	4		T14	55
valid_sources[0x43]	2247	1			T2	3		T7	5		T15	3
valid_sources[0x44]	1939	1			T2	1		T6	23		T31	2
valid_sources[0x45]	1687	1			T2	1		T3	2		T7	6
valid_sources[0x46]	1602	1			T8	1		T10	1		T15	10
valid_sources[0x47]	1606	1			T7	2		T32	1		T15	5
valid_sources[0x48]	1753	1			T7	8		T31	1		T32	2
valid_sources[0x49]	2139	1			T3	1		T7	1		T8	2
valid_sources[0x4a]	1658	1			T7	2		T23	1		T31	1
valid_sources[0x4b]	1671	1			T7	3		T8	1		T31	3
valid_sources[0x4c]	1814	1			T7	5		T15	2		T61	1
valid_sources[0x4d]	2735	1			T3	3		T8	1		T23	2
valid_sources[0x4e]	1824	1			T7	3		T33	5		T36	5
valid_sources[0x4f]	1741	1			T7	3		T31	1		T34	1
valid_sources[0x50]	1884	1			T3	2		T7	4		T42	2
valid_sources[0x51]	2594	1			T3	3		T7	3		T8	3
valid_sources[0x52]	1915	1			T2	2		T7	1		T8	4
valid_sources[0x53]	1567	1			T7	6		T8	3		T38	6
valid_sources[0x54]	3109	1			T3	8		T20	2		T31	1
valid_sources[0x55]	2380	1			T2	1		T7	4		T8	5
valid_sources[0x56]	1888	1			T7	2		T23	1		T42	1
valid_sources[0x57]	1633	1			T3	4		T7	2		T8	2
valid_sources[0x58]	2217	1			T3	1		T7	3		T8	1
valid_sources[0x59]	1609	1			T7	5		T32	1		T34	1
valid_sources[0x5a]	1903	1			T3	2		T6	1		T7	4
valid_sources[0x5b]	1897	1			T2	1		T7	1		T31	1
valid_sources[0x5c]	1586	1			T2	1		T7	3		T23	1
valid_sources[0x5d]	2069	1			T23	1		T15	12		T16	2
valid_sources[0x5e]	1678	1			T6	4		T7	4		T34	1
valid_sources[0x5f]	1837	1			T2	1		T7	3		T31	1
valid_sources[0x60]	1934	1			T2	2		T7	1		T15	2
valid_sources[0x61]	1997	1			T7	1		T8	1		T32	2
valid_sources[0x62]	1652	1			T3	11		T7	5		T8	2
valid_sources[0x63]	1710	1			T2	2		T5	1		T7	1
valid_sources[0x64]	2356	1			T2	1		T7	7		T8	1
valid_sources[0x65]	2434	1			T7	5		T8	5		T23	1
valid_sources[0x66]	1737	1			T2	1		T7	2		T8	1
valid_sources[0x67]	2413	1			T2	1		T7	2		T34	1
valid_sources[0x68]	1622	1			T8	1		T15	4		T16	1
valid_sources[0x69]	2264	1			T7	2		T8	6		T31	2
valid_sources[0x6a]	1831	1			T2	1		T5	1		T7	2
valid_sources[0x6b]	1690	1			T7	1		T33	1		T15	14
valid_sources[0x6c]	2712	1			T7	4		T8	3		T32	1
valid_sources[0x6d]	1785	1			T7	1		T15	15		T36	5
valid_sources[0x6e]	1770	1			T3	4		T6	8		T7	3
valid_sources[0x6f]	2489	1			T3	9		T7	4		T8	1
valid_sources[0x70]	2547	1			T2	3		T7	5		T8	3
valid_sources[0x71]	1704	1			T38	5		T15	8		T36	1
valid_sources[0x72]	1816	1			T2	1		T7	3		T8	1
valid_sources[0x73]	1784	1			T2	1		T3	5		T7	4
valid_sources[0x74]	2453	1			T2	1		T7	2		T33	2
valid_sources[0x75]	1774	1			T2	1		T7	3		T31	2
valid_sources[0x76]	1620	1			T1	3		T2	1		T7	3
valid_sources[0x77]	1564	1			T3	9		T7	2		T8	1
valid_sources[0x78]	1531	1			T2	2		T7	8		T8	5
valid_sources[0x79]	1863	1			T2	1		T7	5		T32	1
valid_sources[0x7a]	1680	1			T7	5		T23	1		T15	5
valid_sources[0x7b]	1740	1			T2	1		T3	2		T7	4
valid_sources[0x7c]	2011	1			T2	1		T3	2		T7	4
valid_sources[0x7d]	1987	1			T7	2		T8	4		T23	1
valid_sources[0x7e]	2576	1			T7	3		T31	1		T15	17
valid_sources[0x7f]	2488	1			T3	1		T6	2		T7	1
valid_sources[0x80]	1590	1			T7	5		T8	1		T33	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75555

1

T1

21

T2

13

T3

23

values[0x0]

all_enables

biggest_size

46931

1

T1

3

T2

12

T3

25

values[0x1]

all_enables

biggest_size

26771

1

T1

4

T2

7

T3

9