Group : dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg
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Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 35188 1 T7 318 T9 396 T14 2
others[1] 34955 1 T7 289 T9 391 T36 385
others[2] 35130 1 T7 284 T9 417 T36 394
others[3] 58225 1 T7 519 T9 650 T36 682
false 14361 1 T5 2 T7 50 T9 50
true 22994 1 T1 1 T2 1 T3 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 34785 1 T7 306 T9 400 T36 409
others[1] 35197 1 T7 287 T9 376 T36 410
others[2] 34986 1 T7 295 T9 395 T36 390
others[3] 58692 1 T7 510 T9 676 T36 668
false 9797 1 T5 1 T7 50 T9 50
true 18456 1 T1 1 T2 1 T3 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 536 1 T2 1 T8 5 T14 1
others[1] 566 1 T2 1 T8 5 T31 1
others[2] 554 1 T8 3 T15 4 T35 7
others[3] 938 1 T8 12 T23 3 T31 1
false 10325 1 T1 1 T2 14 T3 1
true 2730 1 T2 11 T8 2 T14 3

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