Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

32                      
33         1/1            always_comb reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T42,T15,T36

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	17187543	4905	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	17187543	210736	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	17187543	6997584	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	17187543	210705	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	17187543	4905	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	17187543	210736	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	17187543	6997584	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	17187543	210705	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	4905	0	0
T1	1469	1	0	0
T2	6613	0	0	0
T3	16153	0	0	0
T4	2143	0	0	0
T5	1326	1	0	0
T6	1552	0	0	0
T7	20478	26	0	0
T8	4160	0	0	0
T9	22338	22	0	0
T10	523	0	0	0
T15	0	17	0	0
T27	0	24	0	0
T30	0	1	0	0
T36	0	22	0	0
T42	0	2	0	0
T45	0	3	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	210736	0	0
T1	1469	14	0	0
T2	6613	0	0	0
T3	16153	0	0	0
T4	2143	0	0	0
T5	1326	12	0	0
T6	1552	0	0	0
T7	20478	635	0	0
T8	4160	0	0	0
T9	22338	478	0	0
T10	523	0	0	0
T15	0	465	0	0
T27	0	1361	0	0
T30	0	9	0	0
T36	0	990	0	0
T42	0	438	0	0
T45	0	249	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	6997584	0	0
T1	1469	991	0	0
T2	6613	0	0	0
T3	16153	9307	0	0
T4	2143	1521	0	0
T5	1326	1054	0	0
T6	1552	256	0	0
T7	20478	11479	0	0
T8	4160	0	0	0
T9	22338	11110	0	0
T10	523	0	0	0
T30	0	1324	0	0
T32	0	266	0	0
T42	0	304	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	210705	0	0
T1	1469	14	0	0
T2	6613	0	0	0
T3	16153	0	0	0
T4	2143	0	0	0
T5	1326	12	0	0
T6	1552	0	0	0
T7	20478	635	0	0
T8	4160	0	0	0
T9	22338	478	0	0
T10	523	0	0	0
T15	0	465	0	0
T27	0	1361	0	0
T30	0	9	0	0
T36	0	986	0	0
T42	0	438	0	0
T45	0	249	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	4905	0	0
T1	1469	1	0	0
T2	6613	0	0	0
T3	16153	0	0	0
T4	2143	0	0	0
T5	1326	1	0	0
T6	1552	0	0	0
T7	20478	26	0	0
T8	4160	0	0	0
T9	22338	22	0	0
T10	523	0	0	0
T15	0	17	0	0
T27	0	24	0	0
T30	0	1	0	0
T36	0	22	0	0
T42	0	2	0	0
T45	0	3	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	210736	0	0
T1	1469	14	0	0
T2	6613	0	0	0
T3	16153	0	0	0
T4	2143	0	0	0
T5	1326	12	0	0
T6	1552	0	0	0
T7	20478	635	0	0
T8	4160	0	0	0
T9	22338	478	0	0
T10	523	0	0	0
T15	0	465	0	0
T27	0	1361	0	0
T30	0	9	0	0
T36	0	990	0	0
T42	0	438	0	0
T45	0	249	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	6997584	0	0
T1	1469	991	0	0
T2	6613	0	0	0
T3	16153	9307	0	0
T4	2143	1521	0	0
T5	1326	1054	0	0
T6	1552	256	0	0
T7	20478	11479	0	0
T8	4160	0	0	0
T9	22338	11110	0	0
T10	523	0	0	0
T30	0	1324	0	0
T32	0	266	0	0
T42	0	304	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	210705	0	0
T1	1469	14	0	0
T2	6613	0	0	0
T3	16153	0	0	0
T4	2143	0	0	0
T5	1326	12	0	0
T6	1552	0	0	0
T7	20478	635	0	0
T8	4160	0	0	0
T9	22338	478	0	0
T10	523	0	0	0
T15	0	465	0	0
T27	0	1361	0	0
T30	0	9	0	0
T36	0	986	0	0
T42	0	438	0	0
T45	0	249	0	0