Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	17707464	15502	0	0
intr_enable_rd_A	17707464	32447	0	0
reset_en_rd_A	17707464	1012	0	0
reset_en_regwen_rd_A	17707464	931	0	0
wake_info_capture_dis_rd_A	17707464	914	0	0
wakeup_en_rd_A	17707464	1586	0	0
wakeup_en_regwen_rd_A	17707464	865	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17707464	15502	0	0
T22	21538	0	0	0
T24	136676	9	0	0
T25	0	101	0	0
T26	0	42	0	0
T47	0	160	0	0
T50	0	171	0	0
T79	0	41	0	0
T80	0	9	0	0
T116	1255	0	0	0
T118	0	68	0	0
T119	0	11	0	0
T120	0	44	0	0
T121	10868	0	0	0
T122	1850	0	0	0
T123	5440	0	0	0
T124	3382	0	0	0
T125	8632	0	0	0
T126	3958	0	0	0
T127	514	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17707464	32447	0	0
T3	16153	75	0	0
T4	2143	0	0	0
T5	1326	0	0	0
T6	1552	0	0	0
T7	20478	0	0	0
T8	4160	118	0	0
T9	22338	0	0	0
T10	523	0	0	0
T13	3251	0	0	0
T24	0	539	0	0
T27	0	123	0	0
T38	2085	0	0	0
T76	0	7	0	0
T78	0	60	0	0
T122	0	14	0	0
T124	0	2	0	0
T128	0	98	0	0
T129	0	10	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17707464	1012	0	0
T22	21538	0	0	0
T24	136676	7	0	0
T51	0	18	0	0
T58	0	17	0	0
T80	0	21	0	0
T82	0	15	0	0
T116	1255	0	0	0
T121	10868	0	0	0
T122	1850	0	0	0
T123	5440	0	0	0
T124	3382	0	0	0
T125	8632	0	0	0
T126	3958	0	0	0
T127	514	0	0	0
T130	0	42	0	0
T131	0	16	0	0
T132	0	21	0	0
T133	0	16	0	0
T134	0	19	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17707464	931	0	0
T22	21538	0	0	0
T24	136676	3	0	0
T51	0	14	0	0
T58	0	22	0	0
T80	0	12	0	0
T82	0	8	0	0
T116	1255	0	0	0
T121	10868	0	0	0
T122	1850	0	0	0
T123	5440	0	0	0
T124	3382	0	0	0
T125	8632	0	0	0
T126	3958	0	0	0
T127	514	0	0	0
T130	0	35	0	0
T131	0	1	0	0
T132	0	9	0	0
T133	0	29	0	0
T134	0	24	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17707464	914	0	0
T22	21538	0	0	0
T24	136676	7	0	0
T51	0	10	0	0
T58	0	19	0	0
T80	0	15	0	0
T82	0	7	0	0
T116	1255	0	0	0
T121	10868	0	0	0
T122	1850	0	0	0
T123	5440	0	0	0
T124	3382	0	0	0
T125	8632	0	0	0
T126	3958	0	0	0
T127	514	0	0	0
T130	0	58	0	0
T131	0	9	0	0
T132	0	17	0	0
T133	0	17	0	0
T134	0	10	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17707464	1586	0	0
T22	21538	0	0	0
T24	136676	7	0	0
T51	0	17	0	0
T58	0	25	0	0
T80	0	14	0	0
T82	0	22	0	0
T116	1255	0	0	0
T121	10868	0	0	0
T122	1850	0	0	0
T123	5440	0	0	0
T124	3382	0	0	0
T125	8632	0	0	0
T126	3958	0	0	0
T127	514	0	0	0
T130	0	23	0	0
T131	0	11	0	0
T132	0	32	0	0
T133	0	26	0	0
T134	0	18	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17707464	865	0	0
T22	21538	0	0	0
T24	136676	2	0	0
T51	0	12	0	0
T58	0	25	0	0
T80	0	7	0	0
T82	0	15	0	0
T116	1255	0	0	0
T121	10868	0	0	0
T122	1850	0	0	0
T123	5440	0	0	0
T124	3382	0	0	0
T125	8632	0	0	0
T126	3958	0	0	0
T127	514	0	0	0
T130	0	37	0	0
T131	0	9	0	0
T132	0	14	0	0
T133	0	11	0	0
T134	0	18	0	0