Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	51562629	104274	0	0
StatusRise_A	51562629	117249	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51562629	104274	0	0
T1	4407	6	0	0
T2	19839	69	0	0
T3	48459	49	0	0
T4	6429	20	0	0
T5	3978	6	0	0
T6	4656	24	0	0
T7	61434	215	0	0
T8	12480	6	0	0
T9	67014	210	0	0
T10	1569	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51562629	117249	0	0
T1	4407	9	0	0
T2	19839	72	0	0
T3	48459	52	0	0
T4	6429	22	0	0
T5	3978	9	0	0
T6	4656	27	0	0
T7	61434	218	0	0
T8	12480	9	0	0
T9	67014	212	0	0
T10	1569	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17187543	38838	0	0
StatusRise_A	17187543	43485	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	38838	0	0
T1	1469	2	0	0
T2	6613	23	0	0
T3	16153	18	0	0
T4	2143	7	0	0
T5	1326	2	0	0
T6	1552	8	0	0
T7	20478	87	0	0
T8	4160	2	0	0
T9	22338	87	0	0
T10	523	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	43485	0	0
T1	1469	3	0	0
T2	6613	24	0	0
T3	16153	19	0	0
T4	2143	8	0	0
T5	1326	3	0	0
T6	1552	9	0	0
T7	20478	88	0	0
T8	4160	3	0	0
T9	22338	88	0	0
T10	523	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17187543	38840	0	0
StatusRise_A	17187543	43488	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	38840	0	0
T1	1469	2	0	0
T2	6613	23	0	0
T3	16153	18	0	0
T4	2143	7	0	0
T5	1326	2	0	0
T6	1552	8	0	0
T7	20478	87	0	0
T8	4160	2	0	0
T9	22338	87	0	0
T10	523	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	43488	0	0
T1	1469	3	0	0
T2	6613	24	0	0
T3	16153	19	0	0
T4	2143	8	0	0
T5	1326	3	0	0
T6	1552	9	0	0
T7	20478	88	0	0
T8	4160	3	0	0
T9	22338	88	0	0
T10	523	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17187543	26596	0	0
StatusRise_A	17187543	30276	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	26596	0	0
T1	1469	2	0	0
T2	6613	23	0	0
T3	16153	13	0	0
T4	2143	6	0	0
T5	1326	2	0	0
T6	1552	8	0	0
T7	20478	41	0	0
T8	4160	2	0	0
T9	22338	36	0	0
T10	523	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	30276	0	0
T1	1469	3	0	0
T2	6613	24	0	0
T3	16153	14	0	0
T4	2143	6	0	0
T5	1326	3	0	0
T6	1552	9	0	0
T7	20478	42	0	0
T8	4160	3	0	0
T9	22338	36	0	0
T10	523	3	0	0