Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

41                      
42         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
43         1/1            always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
           Tests:       T1 T2 T3 
44         1/1            always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	17188108	11249	0	0
EscTimeoutStoppedByClReset_A	17187543	2377327	0	0
EscTimeoutTriggersReset_A	3670404	441	0	0
RomAllowActiveState_A	17187543	43100	0	0
RomAllowCheckGoodState_A	17187543	43150	0	0
RomBlockActiveState_A	17187543	25596	0	0
RomBlockCheckGoodState_A	17187543	349849	0	0
RomIntgChkDisFalse_A	17187543	16622641	0	0
RomIntgChkDisTrue_A	17187543	154031	0	0
RstreqChkEsctimeout_A	17187543	3076	0	0
RstreqChkFsmterm_A	17187543	140	0	0
RstreqChkGlbesc_A	17187543	3076	0	0
RstreqChkMainpd_A	17187543	745349	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17188108	11249	0	0
T11	9857	226	0	0
T15	38663	0	0	0
T20	14387	0	0	0
T23	2968	0	0	0
T30	2134	0	0	0
T31	5871	0	0	0
T32	1454	0	0	0
T33	2112	0	0	0
T34	2038	0	0	0
T39	0	392	0	0
T42	3236	0	0	0
T135	0	4	0	0
T136	0	58	0	0
T137	0	224	0	0
T138	0	514	0	0
T139	0	34	0	0
T140	0	128	0	0
T141	0	105	0	0
T142	0	153	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	2377327	0	0
T1	1469	14	0	0
T2	6613	933	0	0
T3	16153	2189	0	0
T4	2143	154	0	0
T5	1326	12	0	0
T6	1552	5	0	0
T7	20478	2709	0	0
T8	4160	42	0	0
T9	22338	3099	0	0
T10	523	13	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3670404	441	0	0
T10	492	7	0	0
T11	247	6	0	0
T12	0	4	0	0
T13	319	0	0	0
T14	1157	0	0	0
T17	319	0	0	0
T20	15658	0	0	0
T23	1584	0	0	0
T30	184	0	0	0
T38	231	0	0	0
T39	0	5	0	0
T42	314	0	0	0
T127	0	10	0	0
T135	0	4	0	0
T136	0	5	0	0
T137	0	4	0	0
T138	0	6	0	0
T143	0	4	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	43100	0	0
T1	1469	3	0	0
T2	6613	24	0	0
T3	16153	19	0	0
T4	2143	8	0	0
T5	1326	3	0	0
T6	1552	9	0	0
T7	20478	88	0	0
T8	4160	3	0	0
T9	22338	88	0	0
T10	523	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	43150	0	0
T1	1469	3	0	0
T2	6613	24	0	0
T3	16153	19	0	0
T4	2143	8	0	0
T5	1326	3	0	0
T6	1552	9	0	0
T7	20478	88	0	0
T8	4160	3	0	0
T9	22338	88	0	0
T10	523	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	25596	0	0
T7	20478	22	0	0
T8	4160	0	0	0
T9	22338	19	0	0
T10	523	0	0	0
T11	9857	0	0	0
T13	3251	0	0	0
T14	959	0	0	0
T17	3318	0	0	0
T23	2967	0	0	0
T38	2085	0	0	0
T41	0	139	0	0
T144	0	166	0	0
T145	0	13	0	0
T146	0	729	0	0
T147	0	425	0	0
T148	0	671	0	0
T149	0	3	0	0
T150	0	614	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	349849	0	0
T5	1326	23	0	0
T6	1552	0	0	0
T7	20478	1160	0	0
T8	4160	0	0	0
T9	22338	1263	0	0
T10	523	0	0	0
T13	3251	0	0	0
T14	959	0	0	0
T15	0	847	0	0
T17	3318	0	0	0
T27	0	4063	0	0
T34	0	91	0	0
T36	0	2281	0	0
T38	2085	0	0	0
T41	0	6	0	0
T43	0	69	0	0
T78	0	391	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	16622641	0	0
T1	1469	1379	0	0
T2	6613	6554	0	0
T3	16153	16072	0	0
T4	2143	2072	0	0
T5	1326	1268	0	0
T6	1552	1485	0	0
T7	20478	20245	0	0
T8	4160	4096	0	0
T9	22338	22240	0	0
T10	523	375	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	154031	0	0
T7	20478	173	0	0
T8	4160	0	0	0
T9	22338	0	0	0
T10	523	0	0	0
T11	9857	0	0	0
T13	3251	0	0	0
T14	959	233	0	0
T17	3318	0	0	0
T23	2967	0	0	0
T27	0	26856	0	0
T38	2085	0	0	0
T41	0	833	0	0
T144	0	62	0	0
T145	0	619	0	0
T146	0	2660	0	0
T147	0	801	0	0
T151	0	157	0	0
T152	0	193	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	3076	0	0
T2	6613	11	0	0
T3	16153	0	0	0
T4	2143	0	0	0
T5	1326	0	0	0
T6	1552	0	0	0
T7	20478	0	0	0
T8	4160	0	0	0
T9	22338	0	0	0
T10	523	1	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	0	4	0	0
T14	0	1	0	0
T15	0	37	0	0
T20	0	20	0	0
T23	0	5	0	0
T31	0	5	0	0
T38	2085	0	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	140	0	0
T12	1355	0	0	0
T15	38662	0	0	0
T16	1205	0	0	0
T20	14387	40	0	0
T21	0	40	0	0
T22	0	20	0	0
T28	0	20	0	0
T29	0	20	0	0
T30	2134	0	0	0
T31	5871	0	0	0
T32	1453	0	0	0
T33	2111	0	0	0
T34	2037	0	0	0
T35	2999	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	3076	0	0
T2	6613	11	0	0
T3	16153	0	0	0
T4	2143	0	0	0
T5	1326	0	0	0
T6	1552	0	0	0
T7	20478	0	0	0
T8	4160	0	0	0
T9	22338	0	0	0
T10	523	1	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	0	4	0	0
T14	0	1	0	0
T15	0	37	0	0
T20	0	20	0	0
T23	0	5	0	0
T31	0	5	0	0
T38	2085	0	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17187543	745349	0	0
T2	6613	896	0	0
T3	16153	0	0	0
T4	2143	0	0	0
T5	1326	0	0	0
T6	1552	0	0	0
T7	20478	2451	0	0
T8	4160	0	0	0
T9	22338	1456	0	0
T10	523	0	0	0
T14	0	32	0	0
T15	0	2033	0	0
T17	0	20	0	0
T23	0	115	0	0
T27	0	5142	0	0
T31	0	764	0	0
T36	0	3913	0	0
T38	2085	0	0	0