Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24335

1

T3

4

T4

2

T5

3

auto[1]

23032

1

T2

2

T3

2

T5

2

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24499

1

T2

2

T3

2

T4

2

auto[1]

22868

1

T3

4

T5

2

T9

10

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23264

1

T3

2

T5

3

T9

16

auto[1]

24103

1

T2

2

T3

4

T4

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26562

1

T2

1

T3

3

T4

1

auto[1]

20805

1

T2

1

T3

3

T4

1

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23150

1

T3

4

T5

2

T9

8

auto[1]

24217

1

T2

2

T3

2

T4

2

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24431

1

T3

2

T4

2

T5

4

auto[1]

22936

1

T2

2

T3

4

T5

1

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

844

1

T26

1

T15

2

T41

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

657

1

T26

1

T15

2

T41

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

821

1

T15

2

T41

1

T37

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

637

1

T15

2

T41

1

T37

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

847

1

T9

1

T15

1

T36

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

676

1

T9

1

T15

1

T36

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1315

1

T4

1

T9

1

T15

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1140

1

T4

1

T9

1

T15

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

864

1

T3

1

T9

1

T15

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

672

1

T3

1

T9

1

T15

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

815

1

T15

2

T37

3

T33

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

648

1

T15

2

T37

3

T33

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

853

1

T5

1

T9

1

T15

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

658

1

T9

1

T15

1

T37

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

852

1

T9

1

T26

2

T15

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

665

1

T9

1

T26

1

T15

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

778

1

T26

1

T15

1

T62

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

612

1

T15

1

T62

3

T168

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

830

1

T5

2

T26

1

T16

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

635

1

T26

1

T62

2

T80

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

794

1

T26

2

T15

5

T41

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

619

1

T26

1

T15

5

T37

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

789

1

T37

2

T33

4

T36

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

610

1

T37

2

T33

4

T36

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

777

1

T15

1

T37

1

T16

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

608

1

T15

1

T37

1

T62

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

774

1

T3

1

T15

2

T37

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

584

1

T3

1

T15

2

T37

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

864

1

T9

2

T15

4

T37

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

680

1

T9

2

T15

4

T37

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

801

1

T9

1

T15

1

T37

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

616

1

T9

1

T15

1

T37

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

813

1

T15

1

T41

1

T36

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

641

1

T15

1

T36

1

T38

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

828

1

T37

1

T16

1

T38

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

641

1

T37

1

T38

2

T62

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

785

1

T5

2

T9

1

T26

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

606

1

T9

1

T26

1

T15

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

896

1

T26

1

T15

1

T37

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

729

1

T26

1

T15

1

T37

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

812

1

T37

2

T33

1

T16

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

627

1

T37

2

T33

1

T62

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

799

1

T9

1

T15

1

T45

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

616

1

T9

1

T15

1

T62

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

749

1

T9

1

T37

2

T38

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

596

1

T9

1

T37

2

T38

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

782

1

T2

1

T15

2

T37

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

615

1

T2

1

T15

2

T37

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

859

1

T9

1

T15

1

T37

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

665

1

T9

1

T15

1

T37

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

803

1

T9

1

T15

2

T37

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

614

1

T9

1

T15

2

T37

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

841

1

T15

3

T37

1

T33

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

672

1

T15

3

T37

1

T33

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

814

1

T3

1

T26

1

T15

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

620

1

T3

1

T15

1

T37

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

790

1

T26

1

T37

1

T33

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

618

1

T26

1

T37

1

T33

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

830

1

T36

1

T16

1

T166

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

638

1

T36

1

T166

1

T62

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

777

1

T15

2

T37

3

T17

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

610

1

T15

2

T37

3

T62

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

766

1

T15

2

T37

1

T36

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

580

1

T15

2

T37

1

T36

1