Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 98.23 96.58 99.62 96.00 96.37 100.00 99.02


Total tests in report: 1116
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
78.63 78.63 95.74 95.74 85.45 85.45 82.86 82.86 60.00 60.00 92.75 92.75 91.05 91.05 42.55 42.55 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.1215922572
83.15 4.52 95.74 0.00 85.45 0.00 85.12 2.26 60.00 0.00 92.75 0.00 91.32 0.26 71.69 29.13 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2117018984
87.36 4.21 96.14 0.40 85.73 0.29 88.51 3.39 82.00 22.00 93.32 0.57 92.63 1.32 73.16 1.47 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.2409789475
89.63 2.27 96.79 0.64 87.30 1.57 88.98 0.47 86.00 4.00 93.89 0.57 93.42 0.79 81.01 7.86 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.3953376856
91.78 2.15 96.95 0.16 88.45 1.14 98.59 9.60 88.00 2.00 94.66 0.76 94.47 1.05 81.34 0.33 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.1905902262
93.46 1.68 97.27 0.32 90.73 2.28 99.34 0.75 88.00 0.00 94.85 0.19 97.11 2.63 86.91 5.56 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.3777171214
94.69 1.24 97.27 0.00 90.73 0.00 99.34 0.00 96.00 8.00 94.85 0.00 97.11 0.00 87.56 0.65 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.1701416960
95.90 1.20 97.83 0.56 93.87 3.14 99.53 0.19 96.00 0.00 95.61 0.76 97.11 0.00 91.33 3.76 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2633520643
96.25 0.35 97.83 0.00 93.87 0.00 99.53 0.00 96.00 0.00 95.61 0.00 97.11 0.00 93.78 2.45 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2906201715
96.58 0.34 98.07 0.24 94.01 0.14 99.53 0.00 96.00 0.00 95.61 0.00 97.11 0.00 95.74 1.96 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.1181231538
96.84 0.25 98.23 0.16 94.44 0.43 99.62 0.09 96.00 0.00 96.18 0.57 97.63 0.53 95.74 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.412896497
97.06 0.23 98.23 0.00 94.44 0.00 99.62 0.00 96.00 0.00 96.18 0.00 99.21 1.58 95.74 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1265416822
97.27 0.21 98.23 0.00 94.58 0.14 99.62 0.00 96.00 0.00 96.18 0.00 99.21 0.00 97.05 1.31 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.967236120
97.47 0.20 98.23 0.00 96.01 1.43 99.62 0.00 96.00 0.00 96.18 0.00 99.21 0.00 97.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.2192613325
97.65 0.18 98.23 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.37 0.19 99.47 0.26 97.87 0.82 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.4209446404
97.72 0.06 98.23 0.00 96.29 0.29 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.04 0.16 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.3487532759
97.78 0.06 98.23 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.26 98.20 0.16 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.1969422863
97.83 0.05 98.23 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.53 0.33 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_disable_rom_integrity_check.3790273921
97.85 0.02 98.23 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.69 0.16 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.3470972257
97.87 0.02 98.23 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.85 0.16 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.1712961667
97.90 0.02 98.23 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 99.02 0.16 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.338333447
97.92 0.02 98.23 0.00 96.43 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2750648745
97.94 0.02 98.23 0.00 96.58 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.4241920089

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.442184646
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.481652415
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2468516033
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.1809080725
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.2691826370
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1396882341
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.1436387338
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3563591118
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.1127216644
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2710421623
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.3756447466
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3790052590
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1724217750
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1448962784
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.816357934
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.3603393543
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.745122128
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.2414580574
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2110754766
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.2037891672
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.2562603942
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.2198556822
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.1288579136
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.2502576371
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3193570286
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.1481471548
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2274405488
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.1899599053
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.852643741
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1191544001
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.741779230
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.580343789
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2641405855
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.1791742954
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.265613784
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1664675867
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.2275287133
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.2397587167
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2585030161
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1966029022
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2024174162
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2466192484
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.2572029357
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.3577950441
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.124021649
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.2430751590
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.181578482
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.4122353308
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.3767919574
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.724758662
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1873833224
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.3642898373
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.113787942
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.2769509219
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.1133436597
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2656524229
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.2420159155
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3067952926
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.826744740
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.1664568732
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.268820361
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2225144316
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.245827711
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.94188344
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2130079620
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.1533378540
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.427146883
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2529871305
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.2619482314
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.1742805566
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2376282523
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3412370396
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1814437436
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.3880532817
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.862724485
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.634424387
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3247180105
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.1231901406
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.3417876108
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.3586860378
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.3210063413
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.1170620131
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.4017724573
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.3145549113
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.3999314670
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.4134169505
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.3305029966
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.3047828306
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.2344799375
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1459984009
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1671554342
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2840647609
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.481323244
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.1943497079
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.2915684645
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/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.1795818812
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1585755564
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3807452269
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.3282509795
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.768076703
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/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.1385430377
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/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.395150924
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.723183802
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.2160132315
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3347322459
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3651698441
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.1649614877
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.3754472137
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.4210812925
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.718202881
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.775087011
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.3642910392
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.2715505283
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2914978136
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.3080032322
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/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.880511712
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.3852222876
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.1339896245
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.1277538462
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.1217192691
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.489617839
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1553438800
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.3381578714
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.2571412110
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/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.730058081
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.1264478551
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.4256969681
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.302963385
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.2662205954
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.1707130399
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.3211318626
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.553042217
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.1055262099
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.87449183
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1567502742
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.1560879456
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.1074409304
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.1737326830
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.847270193
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3495610383
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.1395977315
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.1878231793
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.3352898213
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.3382471114
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.2557378736
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.1800216770
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.1343859975
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.1621052831
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.711682475
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.2127343937
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.1597590725
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.2602920295
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.2211091561
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.3330576421
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.2704077559
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.2537362601
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.396067175
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2139041364
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2971754334
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.1303703995
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.1949050481
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.3457501943
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.2488051176
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.1290454187
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.1140564502
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.1827921404
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.3825339005
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3180067969
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.1191582865
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.870926409
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.1817358710
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.421559462
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.3397677389
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.3502381235
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.1389603052
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.1832847307
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.708756522
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3831861457
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3580225726
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.2598952368
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.3679916660
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.1272107771
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.864520379
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.2706009167



Total test records in report: 1116
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.2253283557 Aug 23 11:12:17 PM UTC 24 Aug 23 11:12:19 PM UTC 24 50656787 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.3250966450 Aug 23 11:12:17 PM UTC 24 Aug 23 11:12:19 PM UTC 24 28265164 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.3711144342 Aug 23 11:12:17 PM UTC 24 Aug 23 11:12:19 PM UTC 24 77405000 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.3240544748 Aug 23 11:12:17 PM UTC 24 Aug 23 11:12:19 PM UTC 24 31494955 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.1340062259 Aug 23 11:12:17 PM UTC 24 Aug 23 11:12:19 PM UTC 24 25520643 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.412896497 Aug 23 11:12:17 PM UTC 24 Aug 23 11:12:19 PM UTC 24 46667120 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.9428142 Aug 23 11:12:17 PM UTC 24 Aug 23 11:12:19 PM UTC 24 348877415 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.1712961667 Aug 23 11:12:17 PM UTC 24 Aug 23 11:12:19 PM UTC 24 144757238 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.1215922572 Aug 23 11:12:17 PM UTC 24 Aug 23 11:12:19 PM UTC 24 348027249 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.4241920089 Aug 23 11:12:17 PM UTC 24 Aug 23 11:12:19 PM UTC 24 48640289 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.967236120 Aug 23 11:12:17 PM UTC 24 Aug 23 11:12:19 PM UTC 24 138440982 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.2476981099 Aug 23 11:12:17 PM UTC 24 Aug 23 11:12:19 PM UTC 24 197137437 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.2409789475 Aug 23 11:12:17 PM UTC 24 Aug 23 11:12:19 PM UTC 24 165052381 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.1404755363 Aug 23 11:12:17 PM UTC 24 Aug 23 11:12:19 PM UTC 24 54214302 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2117018984 Aug 23 11:12:17 PM UTC 24 Aug 23 11:12:21 PM UTC 24 1034427582 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.1701416960 Aug 23 11:12:19 PM UTC 24 Aug 23 11:12:21 PM UTC 24 44918423 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3635753541 Aug 23 11:12:17 PM UTC 24 Aug 23 11:12:21 PM UTC 24 799022897 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.3727470334 Aug 23 11:12:35 PM UTC 24 Aug 23 11:12:38 PM UTC 24 332961000 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.319310533 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:38 PM UTC 24 56991126 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.803196542 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:38 PM UTC 24 173461115 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.860505305 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:38 PM UTC 24 214539296 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.1363329519 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:43 PM UTC 24 113316590 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.2944216431 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 29033822 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.3227041841 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 49325121 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.2114549211 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:47 PM UTC 24 629491143 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.1859043900 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 68904660 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.160628607 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 303424690 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.3327723697 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 111288120 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.2639098433 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 29671248 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.532988337 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 43667870 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.2649507335 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:46 PM UTC 24 43005909 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.2120849749 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 142297418 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.3512762633 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 172580120 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.1433477426 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 252096551 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.1114058334 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 67003282 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.4079498639 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 38190648 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.2169916114 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 55298958 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.2622034224 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 112101746 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.3775357174 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 85275605 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.328200584 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 118860455 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.1008417383 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 64376533 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.461678909 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:39 PM UTC 24 124806451 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.394854205 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:40 PM UTC 24 714573108 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2989174701 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:40 PM UTC 24 1069099148 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.280542342 Aug 23 11:12:38 PM UTC 24 Aug 23 11:12:40 PM UTC 24 96062959 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.501433277 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:41 PM UTC 24 766770241 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2906201715 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:41 PM UTC 24 924509653 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2219012423 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:42 PM UTC 24 899775125 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.3953376856 Aug 23 11:12:35 PM UTC 24 Aug 23 11:12:42 PM UTC 24 1990061219 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.2082208333 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:42 PM UTC 24 29745635 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.361486759 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:42 PM UTC 24 32310666 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.1492266799 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:42 PM UTC 24 54083952 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.2982889484 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:46 PM UTC 24 139049478 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.2468355708 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:42 PM UTC 24 75689429 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.2099060507 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:43 PM UTC 24 111584373 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.2139150691 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:43 PM UTC 24 42161178 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.2233166544 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:43 PM UTC 24 126781434 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.2129744977 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:43 PM UTC 24 155847840 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.1703480044 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:43 PM UTC 24 56344397 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.2108817915 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:43 PM UTC 24 108597754 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.794066740 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:43 PM UTC 24 275614997 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.2420415129 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:43 PM UTC 24 23031166 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.3988988630 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:43 PM UTC 24 41356757 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.3840592464 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:43 PM UTC 24 43499891 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2189344015 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:43 PM UTC 24 27617700 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.744959528 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:43 PM UTC 24 450864609 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.626975187 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:43 PM UTC 24 337473164 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.292078424 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:43 PM UTC 24 316798993 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.3033073898 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:43 PM UTC 24 348217539 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.3490748876 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:44 PM UTC 24 1282166124 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.1882466208 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:44 PM UTC 24 2090329508 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2557120582 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:44 PM UTC 24 961763046 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.2465702401 Aug 23 11:12:35 PM UTC 24 Aug 23 11:12:45 PM UTC 24 4771240860 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2836613951 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:45 PM UTC 24 863821367 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.2082786766 Aug 23 11:12:43 PM UTC 24 Aug 23 11:12:45 PM UTC 24 118212262 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.24421920 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:45 PM UTC 24 37670786 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.1639797800 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:45 PM UTC 24 41135108 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.4101724992 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:46 PM UTC 24 147712322 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.338333447 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:46 PM UTC 24 60484229 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1780785094 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:46 PM UTC 24 30115786 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.264629561 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:46 PM UTC 24 75559008 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.1861867945 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:46 PM UTC 24 204522123 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.83647679 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:46 PM UTC 24 277458040 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.2208389423 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:46 PM UTC 24 63621715 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.3600341617 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:46 PM UTC 24 114786210 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.1864766586 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:46 PM UTC 24 30606069 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.733976350 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:46 PM UTC 24 308444155 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3048098887 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:47 PM UTC 24 1177393042 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2839296825 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:47 PM UTC 24 1953676330 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.3665764467 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:47 PM UTC 24 603246822 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.4118504246 Aug 23 11:12:46 PM UTC 24 Aug 23 11:12:48 PM UTC 24 103876785 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.1290454187 Aug 23 11:12:56 PM UTC 24 Aug 23 11:12:58 PM UTC 24 136136410 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.1011822962 Aug 23 11:12:46 PM UTC 24 Aug 23 11:12:48 PM UTC 24 58201516 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.2732483231 Aug 23 11:12:46 PM UTC 24 Aug 23 11:12:48 PM UTC 24 211413390 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.3754472137 Aug 23 11:12:47 PM UTC 24 Aug 23 11:12:48 PM UTC 24 29893645 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.1284100022 Aug 23 11:12:46 PM UTC 24 Aug 23 11:12:48 PM UTC 24 61153018 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.2557378736 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:55 PM UTC 24 222482138 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.3211318626 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:55 PM UTC 24 110875351 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.2219920457 Aug 23 11:12:46 PM UTC 24 Aug 23 11:12:48 PM UTC 24 104601806 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.87449183 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:55 PM UTC 24 85121312 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.3345269204 Aug 23 11:12:47 PM UTC 24 Aug 23 11:12:48 PM UTC 24 37054643 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.395150924 Aug 23 11:12:47 PM UTC 24 Aug 23 11:12:49 PM UTC 24 87927020 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.1649614877 Aug 23 11:12:47 PM UTC 24 Aug 23 11:12:49 PM UTC 24 97014557 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1730430864 Aug 23 11:12:47 PM UTC 24 Aug 23 11:12:49 PM UTC 24 30083641 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.1230734736 Aug 23 11:12:47 PM UTC 24 Aug 23 11:12:49 PM UTC 24 59333933 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.1905902262 Aug 23 11:12:46 PM UTC 24 Aug 23 11:12:49 PM UTC 24 684364591 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.1385430377 Aug 23 11:12:47 PM UTC 24 Aug 23 11:12:49 PM UTC 24 128722478 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.3642910392 Aug 23 11:12:47 PM UTC 24 Aug 23 11:12:49 PM UTC 24 230657800 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.775087011 Aug 23 11:12:47 PM UTC 24 Aug 23 11:12:49 PM UTC 24 298266568 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.2160132315 Aug 23 11:12:47 PM UTC 24 Aug 23 11:12:49 PM UTC 24 285845647 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.1123794970 Aug 23 11:12:37 PM UTC 24 Aug 23 11:12:50 PM UTC 24 3752455197 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3347322459 Aug 23 11:12:47 PM UTC 24 Aug 23 11:12:50 PM UTC 24 1209597316 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3651698441 Aug 23 11:12:47 PM UTC 24 Aug 23 11:12:50 PM UTC 24 1269296801 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.55514692 Aug 23 11:12:41 PM UTC 24 Aug 23 11:12:51 PM UTC 24 4682157467 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.1949050481 Aug 23 11:12:56 PM UTC 24 Aug 23 11:12:58 PM UTC 24 59648784 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.18902064 Aug 23 11:12:49 PM UTC 24 Aug 23 11:12:51 PM UTC 24 70706698 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.2577922575 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:51 PM UTC 24 52190915 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.3409495928 Aug 23 11:12:49 PM UTC 24 Aug 23 11:12:51 PM UTC 24 207654006 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.2286974766 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:51 PM UTC 24 84820839 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.723183802 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:51 PM UTC 24 171217527 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.367002065 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:55 PM UTC 24 275534062 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.1339896245 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:51 PM UTC 24 63167029 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.2715505283 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:52 PM UTC 24 39162128 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.2571412110 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:52 PM UTC 24 30471550 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.3605567123 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:52 PM UTC 24 41662275 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.1074409304 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:55 PM UTC 24 120680366 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2914978136 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:52 PM UTC 24 42815401 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.2738551681 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:52 PM UTC 24 35038478 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.3381578714 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:52 PM UTC 24 202079207 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.4209446404 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:52 PM UTC 24 105272594 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.1217192691 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:52 PM UTC 24 223221778 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.3080032322 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:52 PM UTC 24 107695219 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.880511712 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:52 PM UTC 24 45595591 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.1264478551 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:52 PM UTC 24 312565979 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.3852222876 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:52 PM UTC 24 301578332 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.1277538462 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:52 PM UTC 24 98482401 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.4256969681 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:52 PM UTC 24 314976383 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.489617839 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:53 PM UTC 24 1257039701 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.4210812925 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:54 PM UTC 24 1144306521 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.730058081 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:54 PM UTC 24 705878203 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1553438800 Aug 23 11:12:50 PM UTC 24 Aug 23 11:12:54 PM UTC 24 917331362 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.1560879456 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:54 PM UTC 24 38288128 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.1878231793 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:54 PM UTC 24 57000280 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.1707130399 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:55 PM UTC 24 29135179 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.3352898213 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:58 PM UTC 24 2713213397 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.1800216770 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:55 PM UTC 24 190023164 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1567502742 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:55 PM UTC 24 467202826 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.553042217 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:55 PM UTC 24 56991122 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.302963385 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:55 PM UTC 24 68878201 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.1055262099 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:55 PM UTC 24 42916568 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.1395977315 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:55 PM UTC 24 95670218 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.2662205954 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:55 PM UTC 24 63972364 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.2704077559 Aug 23 11:12:56 PM UTC 24 Aug 23 11:12:58 PM UTC 24 118158878 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.1737326830 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:55 PM UTC 24 198636939 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.847270193 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:56 PM UTC 24 876944554 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3495610383 Aug 23 11:12:53 PM UTC 24 Aug 23 11:12:57 PM UTC 24 951940253 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.3606162312 Aug 23 11:13:05 PM UTC 24 Aug 23 11:13:07 PM UTC 24 98965994 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.3330576421 Aug 23 11:12:56 PM UTC 24 Aug 23 11:12:58 PM UTC 24 76185816 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.2602920295 Aug 23 11:12:57 PM UTC 24 Aug 23 11:12:58 PM UTC 24 58614022 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.1597590725 Aug 23 11:12:57 PM UTC 24 Aug 23 11:12:58 PM UTC 24 55917942 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.1140564502 Aug 23 11:12:56 PM UTC 24 Aug 23 11:12:58 PM UTC 24 480130967 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.1343859975 Aug 23 11:12:56 PM UTC 24 Aug 23 11:12:58 PM UTC 24 105596005 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.711682475 Aug 23 11:12:57 PM UTC 24 Aug 23 11:12:58 PM UTC 24 29225408 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.1621052831 Aug 23 11:12:57 PM UTC 24 Aug 23 11:12:59 PM UTC 24 92719143 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.330082531 Aug 23 11:13:10 PM UTC 24 Aug 23 11:13:15 PM UTC 24 265477981 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.1303703995 Aug 23 11:12:57 PM UTC 24 Aug 23 11:12:59 PM UTC 24 67719964 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.2211091561 Aug 23 11:12:57 PM UTC 24 Aug 23 11:12:59 PM UTC 24 54526031 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.2127343937 Aug 23 11:12:57 PM UTC 24 Aug 23 11:12:59 PM UTC 24 110319709 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.2598952368 Aug 23 11:12:57 PM UTC 24 Aug 23 11:12:59 PM UTC 24 31777847 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.396067175 Aug 23 11:12:57 PM UTC 24 Aug 23 11:12:59 PM UTC 24 159283722 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.2537362601 Aug 23 11:12:57 PM UTC 24 Aug 23 11:12:59 PM UTC 24 550438688 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.3502381235 Aug 23 11:12:57 PM UTC 24 Aug 23 11:12:59 PM UTC 24 39904809 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.864520379 Aug 23 11:12:57 PM UTC 24 Aug 23 11:12:59 PM UTC 24 256196765 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.2322811408 Aug 23 11:12:44 PM UTC 24 Aug 23 11:12:59 PM UTC 24 7345416124 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.3397677389 Aug 23 11:12:57 PM UTC 24 Aug 23 11:12:59 PM UTC 24 239344391 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.2706009167 Aug 23 11:12:57 PM UTC 24 Aug 23 11:12:59 PM UTC 24 247165706 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.718202881 Aug 23 11:12:50 PM UTC 24 Aug 23 11:13:00 PM UTC 24 7279579891 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2139041364 Aug 23 11:12:56 PM UTC 24 Aug 23 11:13:00 PM UTC 24 1351683004 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2971754334 Aug 23 11:12:57 PM UTC 24 Aug 23 11:13:00 PM UTC 24 1051461217 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.2332431221 Aug 23 11:12:46 PM UTC 24 Aug 23 11:13:00 PM UTC 24 8085246982 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.1827921404 Aug 23 11:13:00 PM UTC 24 Aug 23 11:13:02 PM UTC 24 113635323 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.4256445271 Aug 23 11:13:05 PM UTC 24 Aug 23 11:13:10 PM UTC 24 893580506 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3180067969 Aug 23 11:13:00 PM UTC 24 Aug 23 11:13:02 PM UTC 24 29588745 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.1832847307 Aug 23 11:13:00 PM UTC 24 Aug 23 11:13:02 PM UTC 24 167136882 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.1276016297 Aug 23 11:13:09 PM UTC 24 Aug 23 11:13:15 PM UTC 24 31057375 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.1817358710 Aug 23 11:13:00 PM UTC 24 Aug 23 11:13:02 PM UTC 24 60396469 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3580225726 Aug 23 11:13:00 PM UTC 24 Aug 23 11:13:02 PM UTC 24 164883897 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.1445206754 Aug 23 11:13:01 PM UTC 24 Aug 23 11:13:02 PM UTC 24 72376549 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.3289681924 Aug 23 11:13:10 PM UTC 24 Aug 23 11:13:15 PM UTC 24 125157642 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.870926409 Aug 23 11:13:00 PM UTC 24 Aug 23 11:13:02 PM UTC 24 61050512 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.3825339005 Aug 23 11:13:00 PM UTC 24 Aug 23 11:13:02 PM UTC 24 59890046 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.1389603052 Aug 23 11:13:00 PM UTC 24 Aug 23 11:13:02 PM UTC 24 113505680 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.648502553 Aug 23 11:13:01 PM UTC 24 Aug 23 11:13:02 PM UTC 24 30344369 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.1191582865 Aug 23 11:13:00 PM UTC 24 Aug 23 11:13:02 PM UTC 24 1353759009 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.421559462 Aug 23 11:13:00 PM UTC 24 Aug 23 11:13:02 PM UTC 24 43082984 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.3457501943 Aug 23 11:12:57 PM UTC 24 Aug 23 11:13:03 PM UTC 24 2526522290 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.777011668 Aug 23 11:13:01 PM UTC 24 Aug 23 11:13:03 PM UTC 24 64093524 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1622702723 Aug 23 11:13:01 PM UTC 24 Aug 23 11:13:03 PM UTC 24 39872926 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.3913255651 Aug 23 11:13:01 PM UTC 24 Aug 23 11:13:03 PM UTC 24 36714353 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.591310329 Aug 23 11:13:01 PM UTC 24 Aug 23 11:13:03 PM UTC 24 487786551 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.4142800585 Aug 23 11:13:01 PM UTC 24 Aug 23 11:13:03 PM UTC 24 66180940 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.2342341050 Aug 23 11:13:01 PM UTC 24 Aug 23 11:13:03 PM UTC 24 231333589 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1658208575 Aug 23 11:13:01 PM UTC 24 Aug 23 11:13:03 PM UTC 24 66961471 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.708756522 Aug 23 11:13:00 PM UTC 24 Aug 23 11:13:03 PM UTC 24 1098881091 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3237179238 Aug 23 11:13:01 PM UTC 24 Aug 23 11:13:04 PM UTC 24 1383825640 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.604027577 Aug 23 11:13:01 PM UTC 24 Aug 23 11:13:04 PM UTC 24 1256242013 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3831861457 Aug 23 11:13:00 PM UTC 24 Aug 23 11:13:04 PM UTC 24 980929491 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.3382471114 Aug 23 11:12:53 PM UTC 24 Aug 23 11:13:05 PM UTC 24 8720891387 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.3679916660 Aug 23 11:13:01 PM UTC 24 Aug 23 11:13:05 PM UTC 24 1551921977 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.783907623 Aug 23 11:13:04 PM UTC 24 Aug 23 11:13:07 PM UTC 24 28746088 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.2641800262 Aug 23 11:13:05 PM UTC 24 Aug 23 11:13:07 PM UTC 24 49625489 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.3126976403 Aug 23 11:13:05 PM UTC 24 Aug 23 11:13:07 PM UTC 24 64626817 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.261306097 Aug 23 11:13:05 PM UTC 24 Aug 23 11:13:07 PM UTC 24 36467367 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.3097058328 Aug 23 11:13:05 PM UTC 24 Aug 23 11:13:07 PM UTC 24 44684804 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.3139226665 Aug 23 11:13:05 PM UTC 24 Aug 23 11:13:07 PM UTC 24 105903943 ps
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T291 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.1664659452 Aug 23 11:13:05 PM UTC 24 Aug 23 11:13:07 PM UTC 24 97036708 ps
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T310 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.2083652401 Aug 23 11:13:10 PM UTC 24 Aug 23 11:13:15 PM UTC 24 78075231 ps
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T312 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.1200575743 Aug 23 11:13:10 PM UTC 24 Aug 23 11:13:15 PM UTC 24 207210583 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.807767676 Aug 23 11:13:10 PM UTC 24 Aug 23 11:13:15 PM UTC 24 189955251 ps
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T317 /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.839282446 Aug 23 11:13:10 PM UTC 24 Aug 23 11:13:16 PM UTC 24 941388321 ps
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