Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

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Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
reset_cross	6	0	6	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12987

1

T1

1

T9

13

T13

5

auto[1]

19517

1

T1

1

T4

1

T9

12

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Summary for Variable reset_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for reset_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27623

1

T1

1

T2

1

T3

3

auto[1]

7562

1

T1

1

T4

1

T9

7

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14513

1

T1

2

T4

1

T6

1

auto[1]

20672

1

T2

1

T3

3

T4

1

---

Summary for Cross reset_cross

Samples crossed: reset_cp enable_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for reset_cross

Bins

reset_cp

enable_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

3245

1

T1

1

T9

4

T13

3

auto[0]

auto[0]

auto[1]

7192

1

T9

7

T15

19

T37

25

auto[0]

auto[1]

auto[0]

3352

1

T9

1

T13

1

T14

4

auto[0]

auto[1]

auto[1]

11153

1

T9

6

T15

31

T37

25

auto[1]

auto[0]

auto[0]

2550

1

T9

2

T13

2

T15

3

auto[1]

auto[1]

auto[0]

5012

1

T1

1

T4

1

T9

5

User Defined Cross Bins for reset_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal	0	Illegal