Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22936 1 T1 2 T3 22 T4 16
auto[1] 22316 1 T3 18 T4 22 T6 6


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22930 1 T1 2 T3 20 T4 22
auto[1] 22322 1 T3 20 T4 16 T6 6


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22086 1 T3 20 T4 30 T6 8
auto[1] 23166 1 T1 2 T3 20 T4 8


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25293 1 T1 1 T3 20 T4 19
auto[1] 19959 1 T1 1 T3 20 T4 19


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22297 1 T3 10 T4 12 T6 7
auto[1] 22955 1 T1 2 T3 30 T4 26


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22997 1 T1 2 T3 20 T4 26
auto[1] 22255 1 T3 20 T4 12 T6 8


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 787 1 T14 1 T87 1 T15 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 603 1 T14 1 T87 1 T39 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 730 1 T4 1 T42 1 T14 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 587 1 T4 1 T42 1 T14 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 734 1 T4 1 T42 1 T14 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 593 1 T4 1 T42 1 T14 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1239 1 T1 1 T3 1 T4 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1070 1 T1 1 T3 1 T4 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 731 1 T3 2 T6 2 T9 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 576 1 T3 2 T9 1 T39 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 779 1 T3 2 T42 1 T14 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 617 1 T3 2 T42 1 T14 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 733 1 T4 2 T9 2 T42 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 582 1 T4 2 T9 2 T42 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 788 1 T6 1 T42 1 T14 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 640 1 T42 1 T14 1 T71 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 809 1 T4 1 T9 1 T15 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 627 1 T4 1 T9 1 T39 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 760 1 T4 1 T6 1 T39 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 602 1 T4 1 T39 2 T40 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 812 1 T3 2 T4 1 T6 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 624 1 T3 2 T4 1 T14 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 748 1 T3 1 T9 1 T39 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 567 1 T3 1 T9 1 T39 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 792 1 T6 1 T14 2 T71 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 632 1 T14 2 T71 1 T39 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 778 1 T14 1 T39 2 T40 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 609 1 T14 1 T39 2 T40 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 800 1 T3 2 T14 2 T15 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 636 1 T3 2 T14 2 T32 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 753 1 T3 1 T9 1 T42 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 598 1 T3 1 T9 1 T40 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 784 1 T4 2 T14 2 T39 3
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 620 1 T4 2 T14 2 T39 3
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 777 1 T6 1 T14 2 T15 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 619 1 T14 2 T39 5 T172 2
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 764 1 T3 1 T4 3 T6 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 593 1 T3 1 T4 3 T9 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 799 1 T3 1 T9 2 T14 3
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 611 1 T3 1 T9 2 T14 3
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 768 1 T3 1 T14 2 T71 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 592 1 T3 1 T14 2 T71 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 821 1 T42 2 T44 1 T14 2
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 644 1 T42 1 T44 1 T14 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 751 1 T3 1 T4 1 T6 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 582 1 T3 1 T4 1 T9 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 790 1 T3 1 T9 3 T42 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 626 1 T3 1 T9 3 T42 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 791 1 T9 1 T42 1 T44 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 627 1 T9 1 T42 1 T44 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 777 1 T14 3 T15 1 T39 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 599 1 T14 3 T39 1 T172 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 765 1 T3 1 T4 2 T9 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 622 1 T3 1 T4 2 T9 2
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 775 1 T3 3 T44 1 T14 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 582 1 T3 3 T14 1 T71 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 762 1 T4 1 T6 1 T42 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 609 1 T4 1 T42 1 T14 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 839 1 T6 1 T42 1 T14 2
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 649 1 T42 1 T14 2 T39 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 775 1 T4 1 T6 1 T9 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 610 1 T4 1 T9 1 T14 2
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 782 1 T4 1 T9 1 T172 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 611 1 T4 1 T9 1 T172 1

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