Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 98.23 96.58 99.62 96.00 96.37 100.00 99.02


Total tests in report: 1054
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
81.06 81.06 95.74 95.74 86.31 86.31 84.09 84.09 60.00 60.00 92.56 92.56 90.79 90.79 57.94 57.94 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.2997437921
85.31 4.25 96.14 0.40 86.59 0.29 87.10 3.01 82.00 22.00 93.13 0.57 92.11 1.32 60.07 2.13 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.3449009095
88.47 3.16 96.79 0.64 86.88 0.29 87.38 0.28 86.00 4.00 93.70 0.57 92.89 0.79 75.61 15.55 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.2900892021
90.62 2.15 96.95 0.16 88.02 1.14 96.99 9.60 88.00 2.00 94.47 0.76 93.95 1.05 75.94 0.33 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.3662341977
92.33 1.72 97.11 0.16 90.73 2.71 97.74 0.75 88.00 0.00 94.66 0.19 96.58 2.63 81.51 5.56 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.651614145
93.77 1.44 97.11 0.00 90.73 0.00 99.25 1.51 88.00 0.00 94.85 0.19 97.11 0.53 89.36 7.86 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4164489231
95.02 1.25 97.83 0.72 93.72 3.00 99.44 0.19 88.00 0.00 95.61 0.76 97.11 0.00 93.45 4.09 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.894427466
96.17 1.14 97.83 0.00 93.72 0.00 99.44 0.00 96.00 8.00 95.61 0.00 97.11 0.00 93.45 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.396400852
96.54 0.37 97.83 0.00 94.01 0.29 99.62 0.19 96.00 0.00 95.61 0.00 97.11 0.00 95.58 2.13 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.2505724542
96.87 0.34 98.07 0.24 94.15 0.14 99.62 0.00 96.00 0.00 95.61 0.00 97.11 0.00 97.55 1.96 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.947027899
97.11 0.24 98.23 0.16 94.58 0.43 99.62 0.00 96.00 0.00 96.18 0.57 97.63 0.53 97.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.2031835336
97.34 0.23 98.23 0.00 94.58 0.00 99.62 0.00 96.00 0.00 96.18 0.00 99.21 1.58 97.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.2135560730
97.50 0.16 98.23 0.00 95.72 1.14 99.62 0.00 96.00 0.00 96.18 0.00 99.21 0.00 97.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.1424944182
97.66 0.16 98.23 0.00 95.72 0.00 99.62 0.00 96.00 0.00 96.37 0.19 99.47 0.26 98.20 0.65 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.735166814
97.71 0.05 98.23 0.00 95.72 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.53 0.33 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.4169201680
97.75 0.04 98.23 0.00 96.01 0.29 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.53 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3104134684
97.79 0.04 98.23 0.00 96.29 0.29 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.53 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.3747083496
97.83 0.04 98.23 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.26 98.53 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3955857807
97.85 0.02 98.23 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.69 0.16 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.1500758856
97.87 0.02 98.23 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.85 0.16 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_disable_rom_integrity_check.2831791298
97.90 0.02 98.23 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 99.02 0.16 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.3539760689
97.92 0.02 98.23 0.00 96.43 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1603495194
97.94 0.02 98.23 0.00 96.58 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.860858392

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.4167978940
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3083428712
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3859225151
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1278229800
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.724909297
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2369980055
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.3095233782
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.680425662
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.383761529
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3001469459
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.2953059200
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.4005041233
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.2755357428
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2705291672
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.3898531920
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1977970897
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.2416861968
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2260049158
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2528947989
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.3099424590
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.649164768
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.2942124136
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.2662418124
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1422534681
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3663670796
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.89775083
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.770904670
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2791007532
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.2240792411
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1525493070
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.1735918192
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.4010352369
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.2139232038
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3786759241
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.3928222064
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.3182719781
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.3304299688
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1907561480
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.583715203
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2323484520
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.897498438
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.2521226066
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.4049007196
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.858313506
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.635754271
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.396011432
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.1615067569
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.1680528261
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.3709538355
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.165526930
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.1328582395
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2497143071
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.409774830
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.3329903203
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.2935119492
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2169545950
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.3512879076
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3954002243
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3043181056
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.764369286
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.42655208
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.3367145386
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.19943861
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.2083153542
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.4228098117
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.879110325
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.2786663864
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1809238709
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.387273273
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.1707664520
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.636748733
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3229169335
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1730607457
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.849391284
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.2113287237
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.666831324
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3488996969
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.2594815337
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.575464576
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.1983924486
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.4185258971
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.861354755
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.2709478871
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.3362476835
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.1392098327
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.170037044
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.3922379587
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.1731835374
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1838513051
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1174504012
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.694247471
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.2839447829
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.3429586822
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.303953198
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.261385432
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.3341540338
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/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.4134414505
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.4055988015
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.3224216655
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.1582999764
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.4008168349
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1052912213
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3859658760
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3180834828
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.921525695
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.1510698620
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.1594591802
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.2852481426
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.1273048311
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.2578662228
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.1411669336
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.3782342672
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.3100108521
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.3943699955
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.4247345400
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.4131876116
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.1736391242
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.3031941940
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.215434974
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2463807049
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2064245141
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.4174392276
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.2630797358
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.1019569171
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.1422984422
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.3777363268
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.466223568
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.3719046638
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.2933273435
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.846432641
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.84935114
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.590946447
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.573390761
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.3848539306
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.3338126370
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.1018376535
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.2272141883
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.1251790448
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2204695255
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2342475171
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.433818508
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.1181434929
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.889914112
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.2154848782
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.2995665765
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.3683786132



Total test records in report: 1054
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.1386509033 Aug 25 06:45:20 AM UTC 24 Aug 25 06:45:23 AM UTC 24 56731507 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.2620708021 Aug 25 06:45:21 AM UTC 24 Aug 25 06:45:24 AM UTC 24 39073296 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.3081161259 Aug 25 06:45:21 AM UTC 24 Aug 25 06:45:24 AM UTC 24 318506570 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.2784403481 Aug 25 06:45:21 AM UTC 24 Aug 25 06:45:24 AM UTC 24 339305591 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.3507111994 Aug 25 06:45:23 AM UTC 24 Aug 25 06:45:25 AM UTC 24 30353874 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.2727572142 Aug 25 06:45:23 AM UTC 24 Aug 25 06:45:25 AM UTC 24 29842558 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.3000978167 Aug 25 06:45:23 AM UTC 24 Aug 25 06:45:25 AM UTC 24 188046957 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.4135075221 Aug 25 06:45:37 AM UTC 24 Aug 25 06:45:40 AM UTC 24 70561060 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.2997437921 Aug 25 06:45:23 AM UTC 24 Aug 25 06:45:26 AM UTC 24 365125651 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.2175876324 Aug 25 06:45:24 AM UTC 24 Aug 25 06:45:26 AM UTC 24 59293308 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.4045784683 Aug 25 06:45:24 AM UTC 24 Aug 25 06:45:26 AM UTC 24 38811951 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.3626907005 Aug 25 06:45:24 AM UTC 24 Aug 25 06:45:26 AM UTC 24 246044716 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.4129319356 Aug 25 06:45:24 AM UTC 24 Aug 25 06:45:26 AM UTC 24 50948719 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.2031835336 Aug 25 06:45:24 AM UTC 24 Aug 25 06:45:27 AM UTC 24 111912850 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.396400852 Aug 25 06:45:26 AM UTC 24 Aug 25 06:45:28 AM UTC 24 151643210 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.2296190973 Aug 25 06:45:26 AM UTC 24 Aug 25 06:45:28 AM UTC 24 41310968 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4164489231 Aug 25 06:45:23 AM UTC 24 Aug 25 06:45:28 AM UTC 24 1000585540 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.2832997318 Aug 25 06:45:26 AM UTC 24 Aug 25 06:45:28 AM UTC 24 195648271 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.3449009095 Aug 25 06:45:26 AM UTC 24 Aug 25 06:45:28 AM UTC 24 100067166 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.1159319447 Aug 25 06:45:26 AM UTC 24 Aug 25 06:45:28 AM UTC 24 44992994 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.2844132281 Aug 25 06:45:26 AM UTC 24 Aug 25 06:45:29 AM UTC 24 178755753 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.1495937316 Aug 25 06:45:37 AM UTC 24 Aug 25 06:45:40 AM UTC 24 40481857 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.500097495 Aug 25 06:45:23 AM UTC 24 Aug 25 06:45:29 AM UTC 24 855263936 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.3919577921 Aug 25 06:45:37 AM UTC 24 Aug 25 06:45:40 AM UTC 24 198074146 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.1155842462 Aug 25 06:45:28 AM UTC 24 Aug 25 06:45:30 AM UTC 24 23144266 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.4031930546 Aug 25 06:45:28 AM UTC 24 Aug 25 06:45:30 AM UTC 24 163149310 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.614883821 Aug 25 06:45:31 AM UTC 24 Aug 25 06:45:37 AM UTC 24 801321170 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1496738909 Aug 25 06:45:28 AM UTC 24 Aug 25 06:45:30 AM UTC 24 32232359 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.1838277599 Aug 25 06:45:28 AM UTC 24 Aug 25 06:45:30 AM UTC 24 57471104 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.2076426916 Aug 25 06:45:28 AM UTC 24 Aug 25 06:45:30 AM UTC 24 97094377 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.2279273401 Aug 25 06:45:26 AM UTC 24 Aug 25 06:45:30 AM UTC 24 1484997232 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.1387042995 Aug 25 06:45:28 AM UTC 24 Aug 25 06:45:30 AM UTC 24 64974019 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.984777858 Aug 25 06:45:28 AM UTC 24 Aug 25 06:45:30 AM UTC 24 50563615 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.1092171270 Aug 25 06:45:28 AM UTC 24 Aug 25 06:45:30 AM UTC 24 201748902 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.2094510457 Aug 25 06:45:28 AM UTC 24 Aug 25 06:45:31 AM UTC 24 232933122 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.3219889328 Aug 25 06:45:29 AM UTC 24 Aug 25 06:45:31 AM UTC 24 198951102 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.1604787659 Aug 25 06:45:30 AM UTC 24 Aug 25 06:45:32 AM UTC 24 40085758 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.463951318 Aug 25 06:45:29 AM UTC 24 Aug 25 06:45:32 AM UTC 24 107910124 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.1525363290 Aug 25 06:45:30 AM UTC 24 Aug 25 06:45:32 AM UTC 24 197899525 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.1991409304 Aug 25 06:45:30 AM UTC 24 Aug 25 06:45:32 AM UTC 24 29255243 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.1251703788 Aug 25 06:45:30 AM UTC 24 Aug 25 06:45:32 AM UTC 24 65583415 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.1508279510 Aug 25 06:45:30 AM UTC 24 Aug 25 06:45:32 AM UTC 24 253448461 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.1368818772 Aug 25 06:45:30 AM UTC 24 Aug 25 06:45:33 AM UTC 24 154965345 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2846683203 Aug 25 06:45:28 AM UTC 24 Aug 25 06:45:33 AM UTC 24 1013715797 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3750156326 Aug 25 06:45:28 AM UTC 24 Aug 25 06:45:33 AM UTC 24 824234364 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.3089432421 Aug 25 06:45:31 AM UTC 24 Aug 25 06:45:33 AM UTC 24 38837913 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.3234196240 Aug 25 06:45:31 AM UTC 24 Aug 25 06:45:33 AM UTC 24 76575306 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.3696013079 Aug 25 06:45:31 AM UTC 24 Aug 25 06:45:34 AM UTC 24 53859233 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.114999102 Aug 25 06:45:31 AM UTC 24 Aug 25 06:45:34 AM UTC 24 56130348 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.1529281183 Aug 25 06:45:32 AM UTC 24 Aug 25 06:45:34 AM UTC 24 82617841 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.2505724542 Aug 25 06:45:31 AM UTC 24 Aug 25 06:45:34 AM UTC 24 246277108 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.3969353389 Aug 25 06:45:32 AM UTC 24 Aug 25 06:45:34 AM UTC 24 48641205 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.1534081797 Aug 25 06:45:31 AM UTC 24 Aug 25 06:45:34 AM UTC 24 404488085 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.4066431114 Aug 25 06:45:29 AM UTC 24 Aug 25 06:45:34 AM UTC 24 620592310 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.2760297169 Aug 25 06:45:32 AM UTC 24 Aug 25 06:45:34 AM UTC 24 122843397 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.2900892021 Aug 25 06:45:26 AM UTC 24 Aug 25 06:45:34 AM UTC 24 2931428135 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.2585150499 Aug 25 06:45:33 AM UTC 24 Aug 25 06:45:36 AM UTC 24 30030489 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.1176609740 Aug 25 06:45:33 AM UTC 24 Aug 25 06:45:36 AM UTC 24 104902218 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.3069481587 Aug 25 06:45:33 AM UTC 24 Aug 25 06:45:36 AM UTC 24 46478498 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.285464949 Aug 25 06:45:33 AM UTC 24 Aug 25 06:45:36 AM UTC 24 92389865 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.582633164 Aug 25 06:45:33 AM UTC 24 Aug 25 06:45:36 AM UTC 24 345157187 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.648310660 Aug 25 06:45:33 AM UTC 24 Aug 25 06:45:36 AM UTC 24 366544884 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.817416272 Aug 25 06:45:33 AM UTC 24 Aug 25 06:45:36 AM UTC 24 185780652 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.631757545 Aug 25 06:45:31 AM UTC 24 Aug 25 06:45:37 AM UTC 24 981661362 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2814075922 Aug 25 06:45:35 AM UTC 24 Aug 25 06:45:37 AM UTC 24 36457886 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.738875591 Aug 25 06:45:35 AM UTC 24 Aug 25 06:45:37 AM UTC 24 41920681 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.2628849383 Aug 25 06:45:35 AM UTC 24 Aug 25 06:45:37 AM UTC 24 35735230 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2746182473 Aug 25 06:45:35 AM UTC 24 Aug 25 06:45:38 AM UTC 24 82405435 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.1156640083 Aug 25 06:45:35 AM UTC 24 Aug 25 06:45:38 AM UTC 24 73783473 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.2998142390 Aug 25 06:45:35 AM UTC 24 Aug 25 06:45:38 AM UTC 24 121685988 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.1038316987 Aug 25 06:45:35 AM UTC 24 Aug 25 06:45:38 AM UTC 24 161280357 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.3181438963 Aug 25 06:45:35 AM UTC 24 Aug 25 06:45:38 AM UTC 24 57881321 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.2183106163 Aug 25 06:45:35 AM UTC 24 Aug 25 06:45:38 AM UTC 24 518962540 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.3944807366 Aug 25 06:45:36 AM UTC 24 Aug 25 06:45:38 AM UTC 24 32237417 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.1231491542 Aug 25 06:45:33 AM UTC 24 Aug 25 06:45:39 AM UTC 24 637003920 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.861202372 Aug 25 06:45:35 AM UTC 24 Aug 25 06:45:39 AM UTC 24 2762578269 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.4036588319 Aug 25 06:45:35 AM UTC 24 Aug 25 06:45:39 AM UTC 24 873060780 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3660004524 Aug 25 06:45:35 AM UTC 24 Aug 25 06:45:40 AM UTC 24 821955930 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.1064189105 Aug 25 06:45:37 AM UTC 24 Aug 25 06:45:40 AM UTC 24 177543504 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.3654081235 Aug 25 06:45:37 AM UTC 24 Aug 25 06:45:40 AM UTC 24 483045615 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1284546600 Aug 25 06:45:39 AM UTC 24 Aug 25 06:45:41 AM UTC 24 30473714 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.3140711447 Aug 25 06:45:39 AM UTC 24 Aug 25 06:45:41 AM UTC 24 60437058 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.583103479 Aug 25 06:45:39 AM UTC 24 Aug 25 06:45:42 AM UTC 24 163133215 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.1534961644 Aug 25 06:45:39 AM UTC 24 Aug 25 06:45:42 AM UTC 24 50259443 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.3337595298 Aug 25 06:45:39 AM UTC 24 Aug 25 06:45:42 AM UTC 24 80221249 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.2277509845 Aug 25 06:45:39 AM UTC 24 Aug 25 06:45:42 AM UTC 24 46415041 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.2137532324 Aug 25 06:45:39 AM UTC 24 Aug 25 06:45:42 AM UTC 24 66600065 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.3907642705 Aug 25 06:45:39 AM UTC 24 Aug 25 06:45:42 AM UTC 24 1151639720 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.3320212710 Aug 25 06:45:39 AM UTC 24 Aug 25 06:45:42 AM UTC 24 33270015 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.3769311652 Aug 25 06:45:39 AM UTC 24 Aug 25 06:45:42 AM UTC 24 393754464 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.3730109297 Aug 25 06:45:30 AM UTC 24 Aug 25 06:45:42 AM UTC 24 1803433371 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.3350064741 Aug 25 06:45:39 AM UTC 24 Aug 25 06:45:42 AM UTC 24 204048509 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.872768464 Aug 25 06:45:41 AM UTC 24 Aug 25 06:45:44 AM UTC 24 128433178 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.3231348239 Aug 25 06:45:41 AM UTC 24 Aug 25 06:45:44 AM UTC 24 52919739 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.311991992 Aug 25 06:45:41 AM UTC 24 Aug 25 06:45:44 AM UTC 24 408609556 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.2813627037 Aug 25 06:45:41 AM UTC 24 Aug 25 06:45:44 AM UTC 24 32828573 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.3110156855 Aug 25 06:45:41 AM UTC 24 Aug 25 06:45:44 AM UTC 24 31905811 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.130516077 Aug 25 06:45:39 AM UTC 24 Aug 25 06:45:44 AM UTC 24 877478873 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.3527609743 Aug 25 06:45:41 AM UTC 24 Aug 25 06:45:44 AM UTC 24 117305950 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.4057158170 Aug 25 06:45:41 AM UTC 24 Aug 25 06:45:44 AM UTC 24 50762988 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.3662341977 Aug 25 06:45:39 AM UTC 24 Aug 25 06:45:44 AM UTC 24 623135051 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.941864378 Aug 25 06:45:41 AM UTC 24 Aug 25 06:45:44 AM UTC 24 252075020 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.3448358144 Aug 25 06:45:43 AM UTC 24 Aug 25 06:45:45 AM UTC 24 49434140 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.3952942862 Aug 25 06:45:41 AM UTC 24 Aug 25 06:45:45 AM UTC 24 270634026 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.1846725880 Aug 25 06:45:43 AM UTC 24 Aug 25 06:45:45 AM UTC 24 78637036 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.4265638767 Aug 25 06:45:43 AM UTC 24 Aug 25 06:45:45 AM UTC 24 78475748 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.580120563 Aug 25 06:45:43 AM UTC 24 Aug 25 06:45:45 AM UTC 24 164167052 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.4108619847 Aug 25 06:45:43 AM UTC 24 Aug 25 06:45:45 AM UTC 24 113457874 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.1271710168 Aug 25 06:45:43 AM UTC 24 Aug 25 06:45:46 AM UTC 24 84286962 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.4263876999 Aug 25 06:45:43 AM UTC 24 Aug 25 06:45:46 AM UTC 24 235794883 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.2000851955 Aug 25 06:45:43 AM UTC 24 Aug 25 06:45:46 AM UTC 24 100477928 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3074786586 Aug 25 06:45:39 AM UTC 24 Aug 25 06:45:46 AM UTC 24 865687517 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2992344373 Aug 25 06:45:41 AM UTC 24 Aug 25 06:45:46 AM UTC 24 1339236218 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.1602308042 Aug 25 06:45:43 AM UTC 24 Aug 25 06:45:46 AM UTC 24 216922348 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.359156973 Aug 25 06:45:45 AM UTC 24 Aug 25 06:45:47 AM UTC 24 40320319 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.738143692 Aug 25 06:45:43 AM UTC 24 Aug 25 06:45:47 AM UTC 24 283542001 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.2572864596 Aug 25 06:45:45 AM UTC 24 Aug 25 06:45:47 AM UTC 24 88571583 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.2259722479 Aug 25 06:45:44 AM UTC 24 Aug 25 06:45:47 AM UTC 24 36735776 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2653149390 Aug 25 06:45:45 AM UTC 24 Aug 25 06:45:47 AM UTC 24 171570621 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.1960090096 Aug 25 06:45:45 AM UTC 24 Aug 25 06:45:47 AM UTC 24 289621606 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.2614230868 Aug 25 06:45:35 AM UTC 24 Aug 25 06:45:47 AM UTC 24 1638644094 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.932069904 Aug 25 06:45:41 AM UTC 24 Aug 25 06:45:48 AM UTC 24 927188428 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.728035521 Aug 25 06:45:46 AM UTC 24 Aug 25 06:45:48 AM UTC 24 51750011 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.2192728114 Aug 25 06:45:46 AM UTC 24 Aug 25 06:45:48 AM UTC 24 42488802 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.2820478408 Aug 25 06:45:46 AM UTC 24 Aug 25 06:45:48 AM UTC 24 67238783 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.921525695 Aug 25 06:45:46 AM UTC 24 Aug 25 06:45:48 AM UTC 24 56108082 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.1140640800 Aug 25 06:45:46 AM UTC 24 Aug 25 06:45:48 AM UTC 24 152945545 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.2894229951 Aug 25 06:45:43 AM UTC 24 Aug 25 06:45:48 AM UTC 24 1469387500 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.1594591802 Aug 25 06:45:47 AM UTC 24 Aug 25 06:45:49 AM UTC 24 42334372 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.4018526021 Aug 25 06:45:46 AM UTC 24 Aug 25 06:45:49 AM UTC 24 113253631 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.3648640337 Aug 25 06:45:47 AM UTC 24 Aug 25 06:45:49 AM UTC 24 45342108 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.3224216655 Aug 25 06:45:46 AM UTC 24 Aug 25 06:45:49 AM UTC 24 161878095 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.4051131044 Aug 25 06:45:29 AM UTC 24 Aug 25 06:45:49 AM UTC 24 5062457470 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.4055988015 Aug 25 06:45:46 AM UTC 24 Aug 25 06:45:49 AM UTC 24 216928776 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.2852481426 Aug 25 06:45:47 AM UTC 24 Aug 25 06:45:49 AM UTC 24 94207857 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3789393719 Aug 25 06:45:45 AM UTC 24 Aug 25 06:45:49 AM UTC 24 872111666 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.3747083496 Aug 25 06:45:26 AM UTC 24 Aug 25 06:45:50 AM UTC 24 10399532342 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.270634283 Aug 25 06:45:39 AM UTC 24 Aug 25 06:45:50 AM UTC 24 3803937082 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.3575291936 Aug 25 06:45:48 AM UTC 24 Aug 25 06:45:50 AM UTC 24 76690949 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.3616184328 Aug 25 06:45:49 AM UTC 24 Aug 25 06:45:51 AM UTC 24 49456416 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3180834828 Aug 25 06:45:48 AM UTC 24 Aug 25 06:45:51 AM UTC 24 116545776 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.1568434018 Aug 25 06:45:49 AM UTC 24 Aug 25 06:45:51 AM UTC 24 39629131 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.166949781 Aug 25 06:45:44 AM UTC 24 Aug 25 06:45:51 AM UTC 24 754376814 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.4134414505 Aug 25 06:45:49 AM UTC 24 Aug 25 06:45:51 AM UTC 24 42207168 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.735166814 Aug 25 06:45:49 AM UTC 24 Aug 25 06:45:51 AM UTC 24 58881068 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.4008168349 Aug 25 06:45:49 AM UTC 24 Aug 25 06:45:51 AM UTC 24 361596152 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.3517905113 Aug 25 06:45:49 AM UTC 24 Aug 25 06:45:51 AM UTC 24 113209068 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.1582999764 Aug 25 06:45:49 AM UTC 24 Aug 25 06:45:52 AM UTC 24 109510720 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.1736391242 Aug 25 06:45:50 AM UTC 24 Aug 25 06:45:52 AM UTC 24 144966423 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.2630797358 Aug 25 06:45:50 AM UTC 24 Aug 25 06:45:53 AM UTC 24 28930584 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3859658760 Aug 25 06:45:48 AM UTC 24 Aug 25 06:45:53 AM UTC 24 900222390 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.466223568 Aug 25 06:45:51 AM UTC 24 Aug 25 06:45:53 AM UTC 24 51895737 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.1273048311 Aug 25 06:45:51 AM UTC 24 Aug 25 06:45:53 AM UTC 24 60733876 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.1411669336 Aug 25 06:45:51 AM UTC 24 Aug 25 06:45:53 AM UTC 24 30042691 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1052912213 Aug 25 06:45:48 AM UTC 24 Aug 25 06:45:53 AM UTC 24 819226447 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.3943699955 Aug 25 06:45:51 AM UTC 24 Aug 25 06:45:53 AM UTC 24 56561101 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.4131876116 Aug 25 06:45:50 AM UTC 24 Aug 25 06:45:53 AM UTC 24 151628002 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.4174392276 Aug 25 06:45:51 AM UTC 24 Aug 25 06:45:53 AM UTC 24 75399455 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.2567522638 Aug 25 06:45:33 AM UTC 24 Aug 25 06:45:53 AM UTC 24 5335654242 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.3777363268 Aug 25 06:45:51 AM UTC 24 Aug 25 06:45:53 AM UTC 24 202267245 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.3782342672 Aug 25 06:45:51 AM UTC 24 Aug 25 06:45:53 AM UTC 24 387663790 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.215434974 Aug 25 06:45:51 AM UTC 24 Aug 25 06:45:53 AM UTC 24 185954075 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.2747843660 Aug 25 06:46:02 AM UTC 24 Aug 25 06:46:04 AM UTC 24 120453102 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.3100108521 Aug 25 06:45:53 AM UTC 24 Aug 25 06:45:55 AM UTC 24 51363604 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.3807216351 Aug 25 06:46:02 AM UTC 24 Aug 25 06:46:04 AM UTC 24 33295370 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.1510698620 Aug 25 06:45:50 AM UTC 24 Aug 25 06:45:55 AM UTC 24 907790824 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.4247345400 Aug 25 06:45:53 AM UTC 24 Aug 25 06:45:55 AM UTC 24 57653053 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.2578662228 Aug 25 06:45:53 AM UTC 24 Aug 25 06:45:55 AM UTC 24 73118220 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.3031941940 Aug 25 06:45:53 AM UTC 24 Aug 25 06:45:55 AM UTC 24 495347574 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.1181434929 Aug 25 06:45:53 AM UTC 24 Aug 25 06:45:55 AM UTC 24 26155241 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.3719046638 Aug 25 06:45:53 AM UTC 24 Aug 25 06:45:55 AM UTC 24 120435590 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.1018376535 Aug 25 06:45:53 AM UTC 24 Aug 25 06:45:55 AM UTC 24 106247852 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.3338126370 Aug 25 06:45:53 AM UTC 24 Aug 25 06:45:55 AM UTC 24 115758292 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.3683786132 Aug 25 06:45:53 AM UTC 24 Aug 25 06:45:55 AM UTC 24 87155777 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.2995665765 Aug 25 06:45:53 AM UTC 24 Aug 25 06:45:55 AM UTC 24 581130965 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2064245141 Aug 25 06:45:51 AM UTC 24 Aug 25 06:45:56 AM UTC 24 877489428 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.433818508 Aug 25 06:45:53 AM UTC 24 Aug 25 06:45:56 AM UTC 24 62349123 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.3005117191 Aug 25 06:45:46 AM UTC 24 Aug 25 06:45:56 AM UTC 24 3257520827 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2463807049 Aug 25 06:45:51 AM UTC 24 Aug 25 06:45:57 AM UTC 24 781500464 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.573390761 Aug 25 06:45:55 AM UTC 24 Aug 25 06:45:57 AM UTC 24 86548469 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.846432641 Aug 25 06:45:55 AM UTC 24 Aug 25 06:45:57 AM UTC 24 29453879 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.590946447 Aug 25 06:45:55 AM UTC 24 Aug 25 06:45:57 AM UTC 24 248170310 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.1251790448 Aug 25 06:45:55 AM UTC 24 Aug 25 06:45:57 AM UTC 24 234354237 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.2933273435 Aug 25 06:45:55 AM UTC 24 Aug 25 06:45:57 AM UTC 24 56890011 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.441050644 Aug 25 06:45:55 AM UTC 24 Aug 25 06:45:57 AM UTC 24 55857776 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.2433964767 Aug 25 06:46:00 AM UTC 24 Aug 25 06:46:02 AM UTC 24 452628397 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.1991219087 Aug 25 06:46:02 AM UTC 24 Aug 25 06:46:04 AM UTC 24 79183723 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.3848539306 Aug 25 06:45:55 AM UTC 24 Aug 25 06:45:57 AM UTC 24 107348158 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.84935114 Aug 25 06:45:55 AM UTC 24 Aug 25 06:45:57 AM UTC 24 200240868 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.2272141883 Aug 25 06:45:55 AM UTC 24 Aug 25 06:45:57 AM UTC 24 153308211 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.2678052684 Aug 25 06:45:55 AM UTC 24 Aug 25 06:45:57 AM UTC 24 92159904 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.3260114690 Aug 25 06:45:56 AM UTC 24 Aug 25 06:45:57 AM UTC 24 28249762 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.2449294224 Aug 25 06:45:55 AM UTC 24 Aug 25 06:45:58 AM UTC 24 80605588 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.2365510363 Aug 25 06:45:55 AM UTC 24 Aug 25 06:45:58 AM UTC 24 118576810 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2204695255 Aug 25 06:45:53 AM UTC 24 Aug 25 06:45:58 AM UTC 24 900394141 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.1019569171 Aug 25 06:45:53 AM UTC 24 Aug 25 06:45:59 AM UTC 24 2511406097 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.2590625926 Aug 25 06:45:55 AM UTC 24 Aug 25 06:45:59 AM UTC 24 298437597 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.889914112 Aug 25 06:45:55 AM UTC 24 Aug 25 06:45:59 AM UTC 24 307786983 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.3129118068 Aug 25 06:45:57 AM UTC 24 Aug 25 06:45:59 AM UTC 24 50885922 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.2298102841 Aug 25 06:45:43 AM UTC 24 Aug 25 06:45:59 AM UTC 24 5804693614 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.860858392 Aug 25 06:45:57 AM UTC 24 Aug 25 06:45:59 AM UTC 24 76216811 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2342475171 Aug 25 06:45:53 AM UTC 24 Aug 25 06:45:59 AM UTC 24 900611505 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.3740195681 Aug 25 06:45:57 AM UTC 24 Aug 25 06:45:59 AM UTC 24 38742582 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup.3196479570 Aug 25 06:46:03 AM UTC 24 Aug 25 06:46:05 AM UTC 24 90298182 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1916338399 Aug 25 06:45:57 AM UTC 24 Aug 25 06:45:59 AM UTC 24 94882034 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2985008651 Aug 25 06:45:56 AM UTC 24 Aug 25 06:45:59 AM UTC 24 1030443970 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.1965114739 Aug 25 06:45:57 AM UTC 24 Aug 25 06:46:00 AM UTC 24 168445305 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.465917217 Aug 25 06:45:57 AM UTC 24 Aug 25 06:46:00 AM UTC 24 109961625 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.4036503619 Aug 25 06:45:58 AM UTC 24 Aug 25 06:46:00 AM UTC 24 152381740 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.4169201680 Aug 25 06:45:57 AM UTC 24 Aug 25 06:46:00 AM UTC 24 63907843 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.1404625706 Aug 25 06:45:58 AM UTC 24 Aug 25 06:46:00 AM UTC 24 26544273 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.3959239204 Aug 25 06:45:58 AM UTC 24 Aug 25 06:46:00 AM UTC 24 30303026 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.3816741998 Aug 25 06:45:58 AM UTC 24 Aug 25 06:46:00 AM UTC 24 106765509 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.426163360 Aug 25 06:45:58 AM UTC 24 Aug 25 06:46:00 AM UTC 24 194596752 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.2914892173 Aug 25 06:45:57 AM UTC 24 Aug 25 06:46:00 AM UTC 24 108688559 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.2123813760 Aug 25 06:45:58 AM UTC 24 Aug 25 06:46:01 AM UTC 24 338272300 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.1925038407 Aug 25 06:45:59 AM UTC 24 Aug 25 06:46:02 AM UTC 24 33510981 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.145176794 Aug 25 06:46:00 AM UTC 24 Aug 25 06:46:02 AM UTC 24 33686695 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.4281076767 Aug 25 06:46:00 AM UTC 24 Aug 25 06:46:02 AM UTC 24 28419285 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.404681597 Aug 25 06:45:35 AM UTC 24 Aug 25 06:46:02 AM UTC 24 6937224239 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.2028229244 Aug 25 06:46:00 AM UTC 24 Aug 25 06:46:02 AM UTC 24 325865123 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2153294734 Aug 25 06:45:59 AM UTC 24 Aug 25 06:46:02 AM UTC 24 147357561 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.2255191210 Aug 25 06:46:00 AM UTC 24 Aug 25 06:46:02 AM UTC 24 81948897 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.2754529738 Aug 25 06:46:00 AM UTC 24 Aug 25 06:46:02 AM UTC 24 42523511 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.2680091239 Aug 25 06:46:00 AM UTC 24 Aug 25 06:46:02 AM UTC 24 61032922 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.1744100605 Aug 25 06:46:00 AM UTC 24 Aug 25 06:46:02 AM UTC 24 59379097 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.4135618077 Aug 25 06:46:00 AM UTC 24 Aug 25 06:46:02 AM UTC 24 168039660 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.2236697 Aug 25 06:46:00 AM UTC 24 Aug 25 06:46:02 AM UTC 24 111649853 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.3437572783 Aug 25 06:46:00 AM UTC 24 Aug 25 06:46:02 AM UTC 24 49544702 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.593043581 Aug 25 06:45:57 AM UTC 24 Aug 25 06:46:03 AM UTC 24 816256454 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.679149422 Aug 25 06:45:59 AM UTC 24 Aug 25 06:46:04 AM UTC 24 862915097 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.1446095070 Aug 25 06:46:02 AM UTC 24 Aug 25 06:46:04 AM UTC 24 43893580 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_smoke.3719003664 Aug 25 06:46:10 AM UTC 24 Aug 25 06:46:12 AM UTC 24 32063959 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1580223655 Aug 25 06:46:02 AM UTC 24 Aug 25 06:46:04 AM UTC 24 38003114 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.520471709 Aug 25 06:46:02 AM UTC 24 Aug 25 06:46:04 AM UTC 24 104919654 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.741317614 Aug 25 06:46:02 AM UTC 24 Aug 25 06:46:04 AM UTC 24 117842876 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.4167196634 Aug 25 06:46:02 AM UTC 24 Aug 25 06:46:04 AM UTC 24 55128592 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.4149980614 Aug 25 06:46:02 AM UTC 24 Aug 25 06:46:04 AM UTC 24 78206264 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.4090166259 Aug 25 06:46:02 AM UTC 24 Aug 25 06:46:05 AM UTC 24 55342753 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.257650851 Aug 25 06:45:46 AM UTC 24 Aug 25 06:46:05 AM UTC 24 9550645797 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.2305877300 Aug 25 06:46:03 AM UTC 24 Aug 25 06:46:05 AM UTC 24 52001909 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.1536405517 Aug 25 06:46:02 AM UTC 24 Aug 25 06:46:05 AM UTC 24 202375510 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.1318403218 Aug 25 06:46:03 AM UTC 24 Aug 25 06:46:05 AM UTC 24 59057460 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.2710751837 Aug 25 06:46:02 AM UTC 24 Aug 25 06:46:05 AM UTC 24 99333847 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.655985223 Aug 25 06:45:58 AM UTC 24 Aug 25 06:46:05 AM UTC 24 1172197620 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.667985004 Aug 25 06:46:03 AM UTC 24 Aug 25 06:46:05 AM UTC 24 68759555 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2755943744 Aug 25 06:46:02 AM UTC 24 Aug 25 06:46:06 AM UTC 24 1909374440 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1227897030 Aug 25 06:45:59 AM UTC 24 Aug 25 06:46:06 AM UTC 24 822955713 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup.2684727094 Aug 25 06:46:12 AM UTC 24 Aug 25 06:46:14 AM UTC 24 92004916 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_aborted_low_power.3113499662 Aug 25 06:46:04 AM UTC 24 Aug 25 06:46:07 AM UTC 24 225752345 ps
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