Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22772

1

T1

2

T3

8

T4

14

auto[1]

21464

1

T3

4

T4

22

T5

4

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22348

1

T1

2

T3

8

T4

12

auto[1]

21888

1

T3

4

T4

24

T5

14

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21767

1

T3

4

T4

18

T5

6

auto[1]

22469

1

T1

2

T3

8

T4

18

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24882

1

T1

1

T3

6

T4

18

auto[1]

19354

1

T1

1

T3

6

T4

18

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21669

1

T3

4

T4

28

T5

12

auto[1]

22567

1

T1

2

T3

8

T4

8

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22495

1

T1

2

T3

8

T4

18

auto[1]

21741

1

T3

4

T4

18

T5

12

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

794

1

T9

2

T43

1

T35

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

619

1

T9

2

T43

1

T35

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

766

1

T3

1

T4

1

T6

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

597

1

T3

1

T4

1

T7

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

751

1

T3

1

T7

1

T9

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

571

1

T3

1

T7

1

T9

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1206

1

T1

1

T5

2

T7

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1035

1

T1

1

T5

2

T7

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

715

1

T4

1

T6

1

T7

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

563

1

T4

1

T7

1

T43

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

745

1

T5

1

T7

2

T9

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

589

1

T5

1

T7

2

T9

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

756

1

T6

1

T7

2

T9

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

606

1

T7

2

T9

1

T34

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

798

1

T7

4

T9

2

T60

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

618

1

T7

4

T9

2

T28

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

812

1

T4

2

T5

1

T6

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

634

1

T4

2

T5

1

T9

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

730

1

T7

2

T9

3

T52

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

560

1

T7

2

T9

3

T35

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

794

1

T6

1

T7

3

T9

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

636

1

T7

3

T9

3

T52

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

769

1

T5

1

T7

1

T9

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

573

1

T5

1

T7

1

T9

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

735

1

T4

2

T5

1

T7

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

566

1

T4

2

T5

1

T7

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

797

1

T3

1

T5

1

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

607

1

T3

1

T5

1

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

813

1

T5

1

T6

1

T9

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

650

1

T5

1

T9

1

T34

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

783

1

T3

1

T4

1

T5

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

584

1

T3

1

T4

1

T5

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

747

1

T7

2

T9

3

T15

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

569

1

T7

2

T9

3

T35

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

771

1

T4

2

T5

1

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

609

1

T4

2

T5

1

T7

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

694

1

T3

1

T6

1

T7

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

537

1

T3

1

T7

2

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

698

1

T3

1

T6

1

T7

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

534

1

T3

1

T7

2

T52

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

771

1

T4

1

T7

1

T9

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

590

1

T4

1

T7

1

T9

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

758

1

T7

3

T9

2

T52

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

606

1

T7

3

T9

2

T52

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

761

1

T7

1

T34

1

T35

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

587

1

T7

1

T34

1

T35

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

780

1

T4

1

T7

6

T9

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

607

1

T4

1

T7

6

T9

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

747

1

T4

2

T7

1

T9

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

586

1

T4

2

T7

1

T9

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

808

1

T7

1

T52

1

T34

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

618

1

T7

1

T52

1

T34

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

780

1

T6

1

T7

2

T9

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

611

1

T7

2

T9

1

T35

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

763

1

T4

2

T6

1

T9

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

576

1

T4

2

T9

1

T34

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

765

1

T4

1

T7

3

T9

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

591

1

T4

1

T7

3

T9

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

742

1

T4

2

T5

1

T7

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

562

1

T4

2

T5

1

T7

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

797

1

T7

1

T9

1

T34

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

619

1

T7

1

T9

1

T34

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

736

1

T7

1

T9

1

T34

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

544

1

T7

1

T9

1

T34

1