Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 98.23 96.58 99.62 96.00 96.37 100.00 98.85


Total tests in report: 1076
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
76.48 76.48 95.74 95.74 78.74 78.74 60.83 60.83 60.00 60.00 92.75 92.75 91.32 91.32 55.97 55.97 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.100834472
85.68 9.20 96.14 0.40 86.02 7.28 86.16 25.33 82.00 22.00 93.32 0.57 92.63 1.32 63.50 7.53 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.1994371287
88.47 2.78 96.95 0.80 88.59 2.57 87.19 1.04 86.00 4.00 94.08 0.76 93.95 1.32 72.50 9.00 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.1260613896
90.69 2.22 97.11 0.16 89.73 1.14 96.80 9.60 88.00 2.00 94.85 0.76 95.00 1.05 73.32 0.82 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.2246236984
92.38 1.69 97.11 0.00 90.16 0.43 97.93 1.13 88.00 0.00 95.04 0.19 95.26 0.26 83.14 9.82 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.3011908153
93.60 1.22 97.83 0.72 93.44 3.28 98.12 0.19 88.00 0.00 95.80 0.76 95.26 0.00 86.74 3.60 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3901380885
94.81 1.21 97.83 0.00 93.44 0.00 98.12 0.00 96.00 8.00 95.80 0.00 95.26 0.00 87.23 0.49 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.4089775400
95.63 0.81 97.83 0.00 93.44 0.00 99.62 1.51 96.00 0.00 95.80 0.00 95.53 0.26 91.16 3.93 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1406439000
95.95 0.32 98.07 0.24 95.29 1.85 99.62 0.00 96.00 0.00 95.80 0.00 95.53 0.00 91.33 0.16 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.2971393944
96.25 0.30 98.07 0.00 95.29 0.00 99.62 0.00 96.00 0.00 95.80 0.00 95.53 0.00 93.45 2.13 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2989830158
96.53 0.28 98.07 0.00 95.29 0.00 99.62 0.00 96.00 0.00 95.80 0.00 95.53 0.00 95.42 1.96 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.2553809562
96.77 0.24 98.23 0.16 95.72 0.43 99.62 0.00 96.00 0.00 96.37 0.57 96.05 0.53 95.42 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.3145335006
97.01 0.23 98.23 0.00 95.86 0.14 99.62 0.00 96.00 0.00 96.37 0.00 97.37 1.32 95.58 0.16 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.338843598
97.23 0.23 98.23 0.00 95.86 0.00 99.62 0.00 96.00 0.00 96.37 0.00 98.95 1.58 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.3451664362
97.42 0.18 98.23 0.00 96.01 0.14 99.62 0.00 96.00 0.00 96.37 0.00 98.95 0.00 96.73 1.15 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.1596629953
97.51 0.10 98.23 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.53 96.89 0.16 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.608927015
97.58 0.07 98.23 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 97.38 0.49 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.2300291341
97.65 0.07 98.23 0.00 96.15 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 97.71 0.33 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2704568047
97.72 0.07 98.23 0.00 96.29 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.04 0.33 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3398866527
97.77 0.05 98.23 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.36 0.33 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_disable_rom_integrity_check.2203618206
97.81 0.04 98.23 0.00 96.43 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.53 0.16 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.410853894
97.85 0.04 98.23 0.00 96.43 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.26 98.53 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.16122188
97.87 0.02 98.23 0.00 96.43 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.69 0.16 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1034730245
97.89 0.02 98.23 0.00 96.43 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.85 0.16 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_disable_rom_integrity_check.136503998
97.91 0.02 98.23 0.00 96.58 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.85 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.695718713

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.4022777018
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3041337159
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.1232099369
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.3074987794
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.4085019280
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1501721065
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.414119404
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2478349686
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1178783653
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.1284745849
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.570547991
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3015707166
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1123841746
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.1180369256
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.2228707340
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.363471587
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.1519328500
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.3627592455
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1154398283
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.1532052684
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.3945562216
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.2851990943
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.3869316128
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1833644167
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2388180642
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.4186660264
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.2717566920
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.4065875164
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.3491320213
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.192757493
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1647707203
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.1243211764
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.3941985730
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3520645943
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.2834517078
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.402733081
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.3165609393
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.70206154
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2913066326
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1981510214
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.330942861
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3860027267
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3568927368
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.2121925117
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.935044349
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.2052284987
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.559405508
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.4267653555
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.1823839464
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.1898727456
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3451725709
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.1696979239
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.890638280
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1910492989
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.1273644567
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.2025112813
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2133066539
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.2291721506
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.804271134
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3272845879
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.1771562149
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.3384569386
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1647741186
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.205836778
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3107923726
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3597393672
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.1757249657
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.3644811008
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1216335027
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.4095312562
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2232943333
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.3116794820
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2336814641
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2611828241
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.3536783747
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.996061954
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.3207343847
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3216006440
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.4098106219
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1373088623
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.1598464067
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.2487716728
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.2489489800
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.2781132696
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.4226870412
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.2262297750
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.3314206690
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.1717737008
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.2933626499
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.3404203098
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.29549025
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/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.1529979701
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.2134587170
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.4292109160
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1234905392
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.3426129551
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.3300607270
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.2639343097
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.3388164358
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.2703520182
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.514658561
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.4125636802
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.3378571954
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3460324088
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3275353326
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2772259091
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.2444562475
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.1059090498
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.741545079
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.3386400094
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.4232682374
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.2382520600
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.3304992683
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.533044086
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.470745930
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.3109399383
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.826093006
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.575394844
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.399344760
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.3785372330
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.3062237673
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.2421985785
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1997107590
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3698911142
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.1154455542
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.843968239
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.3885281924
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.2324015725
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.4091715461
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.2391843951
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.3227036760
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.2124826946
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.1955695404
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.1218156003
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.3705817698
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.1116264986
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.3112346918
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.2637509709
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.772162739
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.999700014
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.50702220
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3849466733
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4022682219
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.1157939828
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.2868578907
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.1601573465
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.302540660
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.45503121
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.76572596
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.628965237
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.1750813920
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.129688129
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.195086486
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.928130247
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.1092569775
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.328146954
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.3070303262
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.1724474524
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3250747402
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3375099078
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1723801884
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2789352138
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.3958487016
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.1545751035
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.1233556363
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.1428892628



Total test records in report: 1076
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.2242401996 Aug 29 10:52:20 AM UTC 24 Aug 29 10:52:23 AM UTC 24 62315437 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.4030471794 Aug 29 10:52:20 AM UTC 24 Aug 29 10:52:23 AM UTC 24 63200556 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.2583524416 Aug 29 10:52:24 AM UTC 24 Aug 29 10:52:26 AM UTC 24 97692734 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.1116436178 Aug 29 10:52:24 AM UTC 24 Aug 29 10:52:27 AM UTC 24 370989190 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.3647725568 Aug 29 10:52:25 AM UTC 24 Aug 29 10:52:28 AM UTC 24 218695141 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.1340060052 Aug 29 10:52:27 AM UTC 24 Aug 29 10:52:30 AM UTC 24 35334176 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1034730245 Aug 29 10:52:27 AM UTC 24 Aug 29 10:52:32 AM UTC 24 2997363393 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2580317364 Aug 29 10:52:31 AM UTC 24 Aug 29 10:52:33 AM UTC 24 177046024 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.100834472 Aug 29 10:52:28 AM UTC 24 Aug 29 10:52:34 AM UTC 24 1594398886 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.3145335006 Aug 29 10:52:32 AM UTC 24 Aug 29 10:52:34 AM UTC 24 29599770 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.3072142731 Aug 29 10:52:33 AM UTC 24 Aug 29 10:52:36 AM UTC 24 50168854 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.1596629953 Aug 29 10:52:33 AM UTC 24 Aug 29 10:52:36 AM UTC 24 286056681 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.3061292539 Aug 29 10:52:34 AM UTC 24 Aug 29 10:52:37 AM UTC 24 113565550 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.3016901810 Aug 29 10:52:35 AM UTC 24 Aug 29 10:52:37 AM UTC 24 40906099 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.2300291341 Aug 29 10:52:35 AM UTC 24 Aug 29 10:52:37 AM UTC 24 57743507 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.1994371287 Aug 29 10:52:35 AM UTC 24 Aug 29 10:52:37 AM UTC 24 152169434 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.4089775400 Aug 29 10:52:36 AM UTC 24 Aug 29 10:52:39 AM UTC 24 45525063 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.2698775987 Aug 29 10:52:36 AM UTC 24 Aug 29 10:52:40 AM UTC 24 999658769 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.3454063077 Aug 29 10:52:39 AM UTC 24 Aug 29 10:52:40 AM UTC 24 62040466 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.1838579033 Aug 29 10:52:39 AM UTC 24 Aug 29 10:52:41 AM UTC 24 75480585 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.3011908153 Aug 29 10:52:39 AM UTC 24 Aug 29 10:52:41 AM UTC 24 406773251 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.4283893 Aug 29 10:52:40 AM UTC 24 Aug 29 10:52:42 AM UTC 24 96148280 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.2168295097 Aug 29 10:52:40 AM UTC 24 Aug 29 10:52:42 AM UTC 24 338052148 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.1398020851 Aug 29 10:52:40 AM UTC 24 Aug 29 10:52:42 AM UTC 24 291402436 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.1102103256 Aug 29 10:52:41 AM UTC 24 Aug 29 10:52:44 AM UTC 24 90564695 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1022720392 Aug 29 10:52:42 AM UTC 24 Aug 29 10:52:44 AM UTC 24 30471749 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.2069981951 Aug 29 10:52:42 AM UTC 24 Aug 29 10:52:44 AM UTC 24 34734365 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.3291176637 Aug 29 10:52:42 AM UTC 24 Aug 29 10:52:45 AM UTC 24 162293793 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.883079172 Aug 29 10:52:42 AM UTC 24 Aug 29 10:52:45 AM UTC 24 1151011143 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.695718713 Aug 29 10:52:44 AM UTC 24 Aug 29 10:52:46 AM UTC 24 48853800 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.3536967094 Aug 29 10:52:44 AM UTC 24 Aug 29 10:52:46 AM UTC 24 110482828 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2989830158 Aug 29 10:52:41 AM UTC 24 Aug 29 10:52:46 AM UTC 24 946574648 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1406439000 Aug 29 10:52:41 AM UTC 24 Aug 29 10:52:46 AM UTC 24 962128087 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.3107265808 Aug 29 10:52:38 AM UTC 24 Aug 29 10:52:47 AM UTC 24 2831107087 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.4268215712 Aug 29 10:52:45 AM UTC 24 Aug 29 10:52:47 AM UTC 24 42602015 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.1824453463 Aug 29 10:52:45 AM UTC 24 Aug 29 10:52:47 AM UTC 24 158830680 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.92910283 Aug 29 10:52:46 AM UTC 24 Aug 29 10:52:48 AM UTC 24 75600828 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.3203547634 Aug 29 10:52:46 AM UTC 24 Aug 29 10:52:48 AM UTC 24 113501965 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.1645201793 Aug 29 10:52:46 AM UTC 24 Aug 29 10:52:49 AM UTC 24 415048293 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.559666605 Aug 29 10:52:47 AM UTC 24 Aug 29 10:52:50 AM UTC 24 32538401 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.4189164900 Aug 29 10:52:47 AM UTC 24 Aug 29 10:52:50 AM UTC 24 205388830 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.3633375130 Aug 29 10:52:45 AM UTC 24 Aug 29 10:52:50 AM UTC 24 629973299 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.608927015 Aug 29 10:52:46 AM UTC 24 Aug 29 10:52:50 AM UTC 24 1518061996 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.1382062606 Aug 29 10:52:49 AM UTC 24 Aug 29 10:52:51 AM UTC 24 30377424 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.2948217383 Aug 29 10:52:47 AM UTC 24 Aug 29 10:52:51 AM UTC 24 319873396 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.2966442851 Aug 29 10:52:49 AM UTC 24 Aug 29 10:52:51 AM UTC 24 73555111 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.549886468 Aug 29 10:52:47 AM UTC 24 Aug 29 10:52:52 AM UTC 24 953502353 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.2883895584 Aug 29 10:52:50 AM UTC 24 Aug 29 10:52:52 AM UTC 24 128343139 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.2747814999 Aug 29 10:52:51 AM UTC 24 Aug 29 10:52:53 AM UTC 24 65803054 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.531907915 Aug 29 10:52:51 AM UTC 24 Aug 29 10:52:53 AM UTC 24 67272337 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.86613868 Aug 29 10:52:51 AM UTC 24 Aug 29 10:52:53 AM UTC 24 91727152 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.2316504593 Aug 29 10:52:51 AM UTC 24 Aug 29 10:52:53 AM UTC 24 203170558 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1069435449 Aug 29 10:52:47 AM UTC 24 Aug 29 10:52:54 AM UTC 24 804593320 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.775289274 Aug 29 10:52:52 AM UTC 24 Aug 29 10:52:54 AM UTC 24 40859228 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.180640680 Aug 29 10:52:52 AM UTC 24 Aug 29 10:52:54 AM UTC 24 353717802 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.3011843638 Aug 29 10:52:53 AM UTC 24 Aug 29 10:52:55 AM UTC 24 47415471 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.3264741304 Aug 29 10:52:53 AM UTC 24 Aug 29 10:52:56 AM UTC 24 91378205 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.2301026782 Aug 29 10:52:53 AM UTC 24 Aug 29 10:52:56 AM UTC 24 33612503 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.2246236984 Aug 29 10:52:52 AM UTC 24 Aug 29 10:52:56 AM UTC 24 922083324 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.3997351404 Aug 29 10:52:54 AM UTC 24 Aug 29 10:52:56 AM UTC 24 257502733 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.2439031155 Aug 29 10:52:55 AM UTC 24 Aug 29 10:52:57 AM UTC 24 164955509 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2059089453 Aug 29 10:52:55 AM UTC 24 Aug 29 10:52:57 AM UTC 24 332769365 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.3512376634 Aug 29 10:52:55 AM UTC 24 Aug 29 10:52:57 AM UTC 24 686523205 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.1260613896 Aug 29 10:52:36 AM UTC 24 Aug 29 10:52:58 AM UTC 24 4972582852 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.3438833722 Aug 29 10:52:56 AM UTC 24 Aug 29 10:52:58 AM UTC 24 33094725 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1344236028 Aug 29 10:52:55 AM UTC 24 Aug 29 10:52:58 AM UTC 24 1442444797 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.908936277 Aug 29 10:52:56 AM UTC 24 Aug 29 10:52:59 AM UTC 24 354272562 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.4025535081 Aug 29 10:52:57 AM UTC 24 Aug 29 10:53:00 AM UTC 24 70601370 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.2590943846 Aug 29 10:52:57 AM UTC 24 Aug 29 10:53:00 AM UTC 24 62806473 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.3337530596 Aug 29 10:52:57 AM UTC 24 Aug 29 10:53:00 AM UTC 24 50315101 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.3332198543 Aug 29 10:52:57 AM UTC 24 Aug 29 10:53:00 AM UTC 24 626799184 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.3110992636 Aug 29 10:52:57 AM UTC 24 Aug 29 10:53:00 AM UTC 24 105027635 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.838638655 Aug 29 10:52:59 AM UTC 24 Aug 29 10:53:01 AM UTC 24 49087397 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2722673798 Aug 29 10:52:55 AM UTC 24 Aug 29 10:53:02 AM UTC 24 865027466 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.212551526 Aug 29 10:52:59 AM UTC 24 Aug 29 10:53:02 AM UTC 24 252364433 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.218693806 Aug 29 10:53:00 AM UTC 24 Aug 29 10:53:02 AM UTC 24 114340472 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.2809125207 Aug 29 10:53:00 AM UTC 24 Aug 29 10:53:02 AM UTC 24 71752279 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.4020948796 Aug 29 10:52:59 AM UTC 24 Aug 29 10:53:02 AM UTC 24 685411616 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.3026464808 Aug 29 10:53:01 AM UTC 24 Aug 29 10:53:03 AM UTC 24 276792865 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.2689046406 Aug 29 10:53:01 AM UTC 24 Aug 29 10:53:03 AM UTC 24 35637231 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.1122472996 Aug 29 10:52:53 AM UTC 24 Aug 29 10:53:03 AM UTC 24 1371868357 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.1994782918 Aug 29 10:53:01 AM UTC 24 Aug 29 10:53:04 AM UTC 24 46382201 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.2977704213 Aug 29 10:53:01 AM UTC 24 Aug 29 10:53:04 AM UTC 24 292675193 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.3877026186 Aug 29 10:53:02 AM UTC 24 Aug 29 10:53:05 AM UTC 24 30199981 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.3616099050 Aug 29 10:52:45 AM UTC 24 Aug 29 10:53:05 AM UTC 24 3422856075 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.3192260379 Aug 29 10:53:02 AM UTC 24 Aug 29 10:53:05 AM UTC 24 63993411 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.754392746 Aug 29 10:53:04 AM UTC 24 Aug 29 10:53:06 AM UTC 24 58575304 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.548173 Aug 29 10:53:04 AM UTC 24 Aug 29 10:53:06 AM UTC 24 85500063 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.3271879265 Aug 29 10:53:04 AM UTC 24 Aug 29 10:53:06 AM UTC 24 73511978 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.896059166 Aug 29 10:53:04 AM UTC 24 Aug 29 10:53:06 AM UTC 24 57247718 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.3773384462 Aug 29 10:53:04 AM UTC 24 Aug 29 10:53:07 AM UTC 24 109034326 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.2546804222 Aug 29 10:53:04 AM UTC 24 Aug 29 10:53:07 AM UTC 24 111334257 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.3170834873 Aug 29 10:53:05 AM UTC 24 Aug 29 10:53:07 AM UTC 24 54517809 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.3367125808 Aug 29 10:53:05 AM UTC 24 Aug 29 10:53:07 AM UTC 24 117562438 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.330476685 Aug 29 10:53:02 AM UTC 24 Aug 29 10:53:08 AM UTC 24 785905376 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3935166685 Aug 29 10:53:02 AM UTC 24 Aug 29 10:53:08 AM UTC 24 941682191 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.3694191047 Aug 29 10:53:05 AM UTC 24 Aug 29 10:53:09 AM UTC 24 328917932 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.1340990108 Aug 29 10:53:07 AM UTC 24 Aug 29 10:53:09 AM UTC 24 85525270 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.606344970 Aug 29 10:53:07 AM UTC 24 Aug 29 10:53:09 AM UTC 24 67423949 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.1529979701 Aug 29 10:53:07 AM UTC 24 Aug 29 10:53:09 AM UTC 24 377744894 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.2637509709 Aug 29 10:53:23 AM UTC 24 Aug 29 10:53:25 AM UTC 24 47415468 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.2400083720 Aug 29 10:53:08 AM UTC 24 Aug 29 10:53:10 AM UTC 24 58306935 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.3091367362 Aug 29 10:53:07 AM UTC 24 Aug 29 10:53:10 AM UTC 24 216746821 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3081117717 Aug 29 10:53:08 AM UTC 24 Aug 29 10:53:10 AM UTC 24 75372663 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.3110224627 Aug 29 10:53:08 AM UTC 24 Aug 29 10:53:11 AM UTC 24 29946273 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.1577467482 Aug 29 10:53:08 AM UTC 24 Aug 29 10:53:11 AM UTC 24 260091200 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.4111271676 Aug 29 10:53:09 AM UTC 24 Aug 29 10:53:11 AM UTC 24 70111027 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.96381519 Aug 29 10:53:09 AM UTC 24 Aug 29 10:53:11 AM UTC 24 84155736 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.2666572270 Aug 29 10:53:09 AM UTC 24 Aug 29 10:53:12 AM UTC 24 48690196 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.3731482392 Aug 29 10:53:09 AM UTC 24 Aug 29 10:53:12 AM UTC 24 115361539 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3563568921 Aug 29 10:53:08 AM UTC 24 Aug 29 10:53:13 AM UTC 24 807971806 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.514658561 Aug 29 10:53:11 AM UTC 24 Aug 29 10:53:14 AM UTC 24 50433062 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.3443121985 Aug 29 10:53:11 AM UTC 24 Aug 29 10:53:14 AM UTC 24 83470485 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.2444562475 Aug 29 10:53:11 AM UTC 24 Aug 29 10:53:14 AM UTC 24 32716014 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.395753652 Aug 29 10:53:05 AM UTC 24 Aug 29 10:53:14 AM UTC 24 1937783605 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.2134587170 Aug 29 10:53:12 AM UTC 24 Aug 29 10:53:14 AM UTC 24 31423454 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.2881362332 Aug 29 10:53:11 AM UTC 24 Aug 29 10:53:14 AM UTC 24 110066189 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.2703520182 Aug 29 10:53:12 AM UTC 24 Aug 29 10:53:14 AM UTC 24 425080813 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.3386400094 Aug 29 10:53:12 AM UTC 24 Aug 29 10:53:14 AM UTC 24 211731199 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.232989818 Aug 29 10:53:08 AM UTC 24 Aug 29 10:53:15 AM UTC 24 911838372 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.4232682374 Aug 29 10:53:12 AM UTC 24 Aug 29 10:53:15 AM UTC 24 216142899 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1234905392 Aug 29 10:53:14 AM UTC 24 Aug 29 10:53:16 AM UTC 24 49786328 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.3904951212 Aug 29 10:52:59 AM UTC 24 Aug 29 10:53:16 AM UTC 24 5150249602 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.2639343097 Aug 29 10:53:15 AM UTC 24 Aug 29 10:53:16 AM UTC 24 63782742 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.3426129551 Aug 29 10:53:15 AM UTC 24 Aug 29 10:53:17 AM UTC 24 430115016 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2772259091 Aug 29 10:53:14 AM UTC 24 Aug 29 10:53:17 AM UTC 24 54680337 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.3378571954 Aug 29 10:53:15 AM UTC 24 Aug 29 10:53:17 AM UTC 24 303983760 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3460324088 Aug 29 10:53:13 AM UTC 24 Aug 29 10:53:18 AM UTC 24 1599746155 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3275353326 Aug 29 10:53:13 AM UTC 24 Aug 29 10:53:18 AM UTC 24 1216171060 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.3300607270 Aug 29 10:53:16 AM UTC 24 Aug 29 10:53:18 AM UTC 24 56770671 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.3388164358 Aug 29 10:53:16 AM UTC 24 Aug 29 10:53:18 AM UTC 24 85099615 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.4292109160 Aug 29 10:53:16 AM UTC 24 Aug 29 10:53:18 AM UTC 24 69090615 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.4125636802 Aug 29 10:53:16 AM UTC 24 Aug 29 10:53:18 AM UTC 24 154358846 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.843968239 Aug 29 10:53:17 AM UTC 24 Aug 29 10:53:19 AM UTC 24 38975703 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.3785372330 Aug 29 10:53:17 AM UTC 24 Aug 29 10:53:20 AM UTC 24 146816793 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.399344760 Aug 29 10:53:17 AM UTC 24 Aug 29 10:53:20 AM UTC 24 629383741 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.4091715461 Aug 29 10:53:17 AM UTC 24 Aug 29 10:53:20 AM UTC 24 142789586 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.3855175543 Aug 29 10:53:11 AM UTC 24 Aug 29 10:53:20 AM UTC 24 1624557546 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.2382520600 Aug 29 10:53:19 AM UTC 24 Aug 29 10:53:21 AM UTC 24 236885553 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.533044086 Aug 29 10:53:19 AM UTC 24 Aug 29 10:53:21 AM UTC 24 30985724 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.1154455542 Aug 29 10:53:19 AM UTC 24 Aug 29 10:53:21 AM UTC 24 75139590 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.826093006 Aug 29 10:53:20 AM UTC 24 Aug 29 10:53:22 AM UTC 24 27620822 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.3109399383 Aug 29 10:53:20 AM UTC 24 Aug 29 10:53:22 AM UTC 24 79650656 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.3304992683 Aug 29 10:53:20 AM UTC 24 Aug 29 10:53:22 AM UTC 24 74003736 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.2391843951 Aug 29 10:53:19 AM UTC 24 Aug 29 10:53:22 AM UTC 24 245794280 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.1059090498 Aug 29 10:53:16 AM UTC 24 Aug 29 10:53:22 AM UTC 24 681740487 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.2421985785 Aug 29 10:53:19 AM UTC 24 Aug 29 10:53:23 AM UTC 24 274617606 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.470745930 Aug 29 10:53:20 AM UTC 24 Aug 29 10:53:23 AM UTC 24 114503505 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.2868578907 Aug 29 10:53:22 AM UTC 24 Aug 29 10:53:23 AM UTC 24 61741388 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.575394844 Aug 29 10:53:21 AM UTC 24 Aug 29 10:53:24 AM UTC 24 43226925 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.3062237673 Aug 29 10:53:21 AM UTC 24 Aug 29 10:53:24 AM UTC 24 122208418 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1997107590 Aug 29 10:53:19 AM UTC 24 Aug 29 10:53:24 AM UTC 24 962295087 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.2553893185 Aug 29 10:53:05 AM UTC 24 Aug 29 10:53:24 AM UTC 24 4934766565 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.302540660 Aug 29 10:53:23 AM UTC 24 Aug 29 10:53:25 AM UTC 24 41460694 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3698911142 Aug 29 10:53:19 AM UTC 24 Aug 29 10:53:24 AM UTC 24 993144541 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.3227036760 Aug 29 10:53:23 AM UTC 24 Aug 29 10:53:25 AM UTC 24 196448053 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.772162739 Aug 29 10:53:23 AM UTC 24 Aug 29 10:53:25 AM UTC 24 117706912 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.45503121 Aug 29 10:53:23 AM UTC 24 Aug 29 10:53:26 AM UTC 24 377727349 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.1955695404 Aug 29 10:53:24 AM UTC 24 Aug 29 10:53:26 AM UTC 24 30959770 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.1116264986 Aug 29 10:53:24 AM UTC 24 Aug 29 10:53:26 AM UTC 24 29517176 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.1157939828 Aug 29 10:53:24 AM UTC 24 Aug 29 10:53:26 AM UTC 24 94114764 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.50702220 Aug 29 10:53:24 AM UTC 24 Aug 29 10:53:27 AM UTC 24 337029085 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.1218156003 Aug 29 10:53:24 AM UTC 24 Aug 29 10:53:27 AM UTC 24 208026012 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.3705817698 Aug 29 10:53:26 AM UTC 24 Aug 29 10:53:28 AM UTC 24 100503141 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.3112346918 Aug 29 10:53:26 AM UTC 24 Aug 29 10:53:28 AM UTC 24 94451468 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.2124826946 Aug 29 10:53:26 AM UTC 24 Aug 29 10:53:28 AM UTC 24 81507628 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3849466733 Aug 29 10:53:23 AM UTC 24 Aug 29 10:53:28 AM UTC 24 795280191 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.3958487016 Aug 29 10:53:26 AM UTC 24 Aug 29 10:53:28 AM UTC 24 57927773 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.999700014 Aug 29 10:53:26 AM UTC 24 Aug 29 10:53:28 AM UTC 24 98981240 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.3731345711 Aug 29 10:53:40 AM UTC 24 Aug 29 10:53:42 AM UTC 24 30435596 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4022682219 Aug 29 10:53:24 AM UTC 24 Aug 29 10:53:29 AM UTC 24 1292639398 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.76572596 Aug 29 10:53:27 AM UTC 24 Aug 29 10:53:29 AM UTC 24 17303383 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.3070303262 Aug 29 10:53:27 AM UTC 24 Aug 29 10:53:29 AM UTC 24 242834301 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.1233556363 Aug 29 10:53:27 AM UTC 24 Aug 29 10:53:29 AM UTC 24 113960700 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.328146954 Aug 29 10:53:27 AM UTC 24 Aug 29 10:53:29 AM UTC 24 213268519 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.1428892628 Aug 29 10:53:27 AM UTC 24 Aug 29 10:53:30 AM UTC 24 185652649 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.1750813920 Aug 29 10:53:29 AM UTC 24 Aug 29 10:53:31 AM UTC 24 30741673 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.928130247 Aug 29 10:53:29 AM UTC 24 Aug 29 10:53:31 AM UTC 24 25502451 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2789352138 Aug 29 10:53:29 AM UTC 24 Aug 29 10:53:31 AM UTC 24 175542640 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.1601573465 Aug 29 10:53:26 AM UTC 24 Aug 29 10:53:31 AM UTC 24 1604018219 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3375099078 Aug 29 10:53:27 AM UTC 24 Aug 29 10:53:32 AM UTC 24 1397601081 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3250747402 Aug 29 10:53:29 AM UTC 24 Aug 29 10:53:32 AM UTC 24 259353360 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.1092569775 Aug 29 10:53:30 AM UTC 24 Aug 29 10:53:32 AM UTC 24 108219615 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.195086486 Aug 29 10:53:30 AM UTC 24 Aug 29 10:53:32 AM UTC 24 39428438 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.628965237 Aug 29 10:53:30 AM UTC 24 Aug 29 10:53:32 AM UTC 24 67601086 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.129688129 Aug 29 10:53:30 AM UTC 24 Aug 29 10:53:32 AM UTC 24 417276567 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.741545079 Aug 29 10:53:16 AM UTC 24 Aug 29 10:53:32 AM UTC 24 14080229652 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.1724474524 Aug 29 10:53:30 AM UTC 24 Aug 29 10:53:32 AM UTC 24 602591709 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.3885281924 Aug 29 10:53:22 AM UTC 24 Aug 29 10:53:33 AM UTC 24 1648891075 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.949527100 Aug 29 10:53:31 AM UTC 24 Aug 29 10:53:33 AM UTC 24 21728022 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.2008526708 Aug 29 10:53:31 AM UTC 24 Aug 29 10:53:33 AM UTC 24 31478058 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.1545751035 Aug 29 10:53:31 AM UTC 24 Aug 29 10:53:33 AM UTC 24 534710861 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1723801884 Aug 29 10:53:29 AM UTC 24 Aug 29 10:53:34 AM UTC 24 813444397 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.3330974106 Aug 29 10:53:33 AM UTC 24 Aug 29 10:53:34 AM UTC 24 57983137 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.2324015725 Aug 29 10:53:22 AM UTC 24 Aug 29 10:53:35 AM UTC 24 7781519537 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.918173506 Aug 29 10:53:33 AM UTC 24 Aug 29 10:53:35 AM UTC 24 39407156 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.3642870611 Aug 29 10:53:33 AM UTC 24 Aug 29 10:53:35 AM UTC 24 203278937 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.3540523152 Aug 29 10:53:33 AM UTC 24 Aug 29 10:53:35 AM UTC 24 94763809 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.3297351900 Aug 29 10:53:33 AM UTC 24 Aug 29 10:53:35 AM UTC 24 183516630 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.46665593 Aug 29 10:53:33 AM UTC 24 Aug 29 10:53:36 AM UTC 24 284708564 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.4090136518 Aug 29 10:53:34 AM UTC 24 Aug 29 10:53:36 AM UTC 24 59193077 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.2213601925 Aug 29 10:53:34 AM UTC 24 Aug 29 10:53:36 AM UTC 24 39386813 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.3213796600 Aug 29 10:53:34 AM UTC 24 Aug 29 10:53:36 AM UTC 24 61021897 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.1317120678 Aug 29 10:53:34 AM UTC 24 Aug 29 10:53:37 AM UTC 24 58808615 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.3728247825 Aug 29 10:53:34 AM UTC 24 Aug 29 10:53:37 AM UTC 24 145531833 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.3822147879 Aug 29 10:53:34 AM UTC 24 Aug 29 10:53:37 AM UTC 24 114914442 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.967026710 Aug 29 10:53:36 AM UTC 24 Aug 29 10:53:38 AM UTC 24 75611573 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.1726761735 Aug 29 10:53:36 AM UTC 24 Aug 29 10:53:38 AM UTC 24 82202156 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2516848020 Aug 29 10:53:33 AM UTC 24 Aug 29 10:53:38 AM UTC 24 933278937 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.1658748604 Aug 29 10:53:36 AM UTC 24 Aug 29 10:53:38 AM UTC 24 55917412 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.3956027996 Aug 29 10:53:36 AM UTC 24 Aug 29 10:53:38 AM UTC 24 168723487 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1890623729 Aug 29 10:53:33 AM UTC 24 Aug 29 10:53:38 AM UTC 24 765123210 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.2254755401 Aug 29 10:53:36 AM UTC 24 Aug 29 10:53:39 AM UTC 24 245736480 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.339474649 Aug 29 10:53:37 AM UTC 24 Aug 29 10:53:39 AM UTC 24 37670886 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.2733001770 Aug 29 10:53:37 AM UTC 24 Aug 29 10:53:39 AM UTC 24 51134765 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.420377186 Aug 29 10:53:37 AM UTC 24 Aug 29 10:53:39 AM UTC 24 32225821 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.147368428 Aug 29 10:53:37 AM UTC 24 Aug 29 10:53:39 AM UTC 24 87861912 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.508478262 Aug 29 10:53:37 AM UTC 24 Aug 29 10:53:39 AM UTC 24 27895125 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.2206759696 Aug 29 10:53:37 AM UTC 24 Aug 29 10:53:40 AM UTC 24 325844339 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.2323744690 Aug 29 10:53:37 AM UTC 24 Aug 29 10:53:40 AM UTC 24 205755732 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.2556769153 Aug 29 10:53:11 AM UTC 24 Aug 29 10:53:40 AM UTC 24 6794985564 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.1114267781 Aug 29 10:53:39 AM UTC 24 Aug 29 10:53:41 AM UTC 24 60818835 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.1387658705 Aug 29 10:53:39 AM UTC 24 Aug 29 10:53:41 AM UTC 24 65823417 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.1840740977 Aug 29 10:53:39 AM UTC 24 Aug 29 10:53:41 AM UTC 24 28975560 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.299155337 Aug 29 10:53:39 AM UTC 24 Aug 29 10:53:41 AM UTC 24 43004216 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.1370327001 Aug 29 10:53:39 AM UTC 24 Aug 29 10:53:41 AM UTC 24 160639124 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.1764006640 Aug 29 10:53:36 AM UTC 24 Aug 29 10:53:41 AM UTC 24 1430436115 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1163597432 Aug 29 10:53:37 AM UTC 24 Aug 29 10:53:42 AM UTC 24 1545221918 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.1526100305 Aug 29 10:53:40 AM UTC 24 Aug 29 10:53:42 AM UTC 24 71507563 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.2061865075 Aug 29 10:53:40 AM UTC 24 Aug 29 10:53:42 AM UTC 24 384969469 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.2590081524 Aug 29 10:53:40 AM UTC 24 Aug 29 10:53:43 AM UTC 24 84433843 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.4216718349 Aug 29 10:53:40 AM UTC 24 Aug 29 10:53:43 AM UTC 24 260825125 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.2870038480 Aug 29 10:53:40 AM UTC 24 Aug 29 10:53:43 AM UTC 24 189101269 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.958180510 Aug 29 10:53:37 AM UTC 24 Aug 29 10:53:44 AM UTC 24 819814464 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.3069100170 Aug 29 10:53:42 AM UTC 24 Aug 29 10:53:44 AM UTC 24 30847288 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.1487632740 Aug 29 10:53:42 AM UTC 24 Aug 29 10:53:44 AM UTC 24 53111219 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.1996661972 Aug 29 10:53:42 AM UTC 24 Aug 29 10:53:44 AM UTC 24 51137651 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.1189656180 Aug 29 10:53:42 AM UTC 24 Aug 29 10:53:44 AM UTC 24 66530384 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.3251593336 Aug 29 10:53:42 AM UTC 24 Aug 29 10:53:44 AM UTC 24 58582799 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.510856641 Aug 29 10:53:42 AM UTC 24 Aug 29 10:53:44 AM UTC 24 246271822 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset.582768764 Aug 29 10:53:53 AM UTC 24 Aug 29 10:53:56 AM UTC 24 122489212 ps
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