Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23135

1

T1

2

T2

2

T4

14

auto[1]

21975

1

T4

8

T5

4

T8

12

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23109

1

T1

2

T4

10

T5

6

auto[1]

22001

1

T2

2

T4

12

T5

3

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22434

1

T4

16

T5

5

T8

6

auto[1]

22676

1

T1

2

T2

2

T4

6

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25366

1

T1

1

T2

1

T4

11

auto[1]

19744

1

T1

1

T2

1

T4

11

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22114

1

T4

12

T5

4

T8

6

auto[1]

22996

1

T1

2

T2

2

T4

10

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23009

1

T1

2

T4

10

T5

6

auto[1]

22101

1

T2

2

T4

12

T5

3

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

808

1

T9

2

T36

1

T34

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

615

1

T36

1

T34

2

T32

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

762

1

T4

1

T5

1

T9

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

584

1

T4

1

T9

1

T34

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

822

1

T9

2

T34

4

T14

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

634

1

T9

1

T34

4

T29

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1190

1

T1

1

T9

5

T34

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1042

1

T1

1

T9

5

T34

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

784

1

T9

3

T148

1

T14

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

614

1

T9

3

T148

1

T29

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

778

1

T9

4

T36

1

T34

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

631

1

T9

2

T36

1

T34

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

793

1

T4

2

T5

2

T9

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

625

1

T4

2

T9

2

T36

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

788

1

T5

1

T8

1

T9

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

616

1

T8

1

T9

3

T24

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

788

1

T4

1

T9

2

T34

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

607

1

T4

1

T9

1

T34

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

799

1

T5

1

T9

5

T39

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

606

1

T9

3

T39

1

T34

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

795

1

T4

2

T8

1

T9

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

616

1

T4

2

T8

1

T9

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

742

1

T8

1

T9

3

T36

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

571

1

T8

1

T9

2

T32

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

801

1

T4

1

T9

3

T24

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

618

1

T4

1

T9

2

T24

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

767

1

T9

4

T34

1

T24

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

568

1

T9

3

T34

1

T24

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

782

1

T9

3

T36

1

T24

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

594

1

T9

2

T36

1

T24

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

782

1

T2

1

T8

1

T9

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

613

1

T2

1

T8

1

T9

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

796

1

T5

2

T8

1

T9

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

633

1

T8

1

T9

1

T36

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

736

1

T8

1

T9

4

T34

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

571

1

T8

1

T9

3

T34

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

786

1

T4

1

T9

2

T34

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

600

1

T4

1

T9

1

T34

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

792

1

T8

1

T9

4

T36

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

608

1

T8

1

T9

4

T34

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

782

1

T9

4

T39

1

T34

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

580

1

T9

2

T39

1

T34

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

801

1

T4

1

T8

1

T9

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

627

1

T4

1

T8

1

T9

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

789

1

T9

1

T36

1

T24

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

611

1

T9

1

T36

1

T24

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

737

1

T9

3

T39

1

T34

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

574

1

T9

2

T34

1

T24

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

799

1

T9

2

T36

1

T34

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

632

1

T9

1

T36

1

T34

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

739

1

T9

1

T34

2

T24

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

569

1

T9

1

T34

2

T24

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

780

1

T5

1

T9

2

T36

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

615

1

T9

2

T36

1

T34

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

786

1

T5

1

T9

2

T34

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

586

1

T34

1

T24

2

T29

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

778

1

T4

1

T9

3

T34

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

601

1

T4

1

T9

3

T34

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

749

1

T4

1

T9

2

T36

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

591

1

T4

1

T9

1

T34

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

756

1

T8

1

T9

2

T36

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

600

1

T8

1

T9

2

T36

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

779

1

T8

1

T9

1

T36

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

592

1

T8

1

T9

1

T36

1