Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 98.23 96.58 99.62 96.00 96.37 100.00 99.02


Total tests in report: 1107
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
84.01 84.01 96.39 96.39 86.88 86.88 84.56 84.56 64.00 64.00 93.32 93.32 91.58 91.58 71.36 71.36 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.3189469244
88.15 4.13 96.79 0.40 87.30 0.43 87.57 3.01 86.00 22.00 93.89 0.57 92.63 1.05 72.83 1.47 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.3350134146
90.34 2.20 96.95 0.16 88.45 1.14 97.18 9.60 88.00 2.00 94.66 0.76 93.68 1.05 73.49 0.65 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.2979840701
92.04 1.70 96.95 0.00 88.45 0.00 98.68 1.51 88.00 0.00 94.66 0.00 93.95 0.26 83.63 10.15 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2821404805
93.40 1.35 97.11 0.16 90.01 1.57 99.44 0.75 88.00 0.00 94.85 0.19 96.32 2.37 88.05 4.42 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.3893273101
94.64 1.25 97.83 0.72 93.30 3.28 99.62 0.19 88.00 0.00 95.61 0.76 96.32 0.00 91.82 3.76 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2559319229
95.78 1.14 97.83 0.00 93.30 0.00 99.62 0.00 96.00 8.00 95.61 0.00 96.32 0.00 91.82 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.1666612745
96.15 0.37 98.07 0.24 95.15 1.85 99.62 0.00 96.00 0.00 95.61 0.00 96.32 0.00 92.31 0.49 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.3686061265
96.46 0.30 98.07 0.00 95.29 0.14 99.62 0.00 96.00 0.00 95.61 0.00 96.32 0.00 94.27 1.96 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.905480907
96.73 0.28 98.23 0.16 95.72 0.43 99.62 0.00 96.00 0.00 96.18 0.57 97.11 0.79 94.27 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.3930191464
96.98 0.25 98.23 0.00 95.72 0.00 99.62 0.00 96.00 0.00 96.18 0.00 98.68 1.58 94.44 0.16 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.1554337761
97.20 0.22 98.23 0.00 95.86 0.14 99.62 0.00 96.00 0.00 96.18 0.00 98.95 0.26 95.58 1.15 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.755150981
97.41 0.21 98.23 0.00 95.86 0.00 99.62 0.00 96.00 0.00 96.37 0.19 99.21 0.26 96.56 0.98 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3896178560
97.57 0.16 98.23 0.00 96.01 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.21 0.00 97.55 0.98 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.3983002005
97.64 0.07 98.23 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.21 0.00 98.04 0.49 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.1139294278
97.71 0.07 98.23 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.21 0.00 98.53 0.49 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.2642947947
97.75 0.04 98.23 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.26 98.53 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.1800702424
97.79 0.04 98.23 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.26 98.53 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.212415254
97.81 0.02 98.23 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.69 0.16 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3369997888
97.83 0.02 98.23 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.85 0.16 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.1252970684
97.86 0.02 98.23 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 99.02 0.16 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.167450855
97.88 0.02 98.23 0.00 96.15 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.503715110
97.90 0.02 98.23 0.00 96.29 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1359429241
97.92 0.02 98.23 0.00 96.43 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2522521584
97.94 0.02 98.23 0.00 96.58 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.1350040683

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.1556326076
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.416730602
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2646043691
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2682916885
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.686700183
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.799456341
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.2037230891
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.1407718630
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2993398165
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2949141860
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.1272975987
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.3410868508
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.1887607506
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.2132845199
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.405972675
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.2930685755
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.3809759147
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3186999702
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.746906342
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.4145705041
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.4230185757
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.3343206745
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.300844971
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.1064658653
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1106401791
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.2795658487
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.3535648883
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3255210116
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.3157664034
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1579379494
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3724540171
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.2937750920
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.4195625447
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.457352539
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.1199848006
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.2417188764
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.1600586321
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.3504928584
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2097137290
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1090682069
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1961694829
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3368752000
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3115353319
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.1278573030
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.678757333
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.3177909276
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2189841156
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2581528741
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.967496233
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.1804017739
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1478686736
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.1218920471
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1655766987
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.1314622922
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.2643139522
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.557883099
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.3082408530
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.894178327
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.4038365582
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.73464981
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.1430820977
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1897292410
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.69175372
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3724471884
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.139483845
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.4057604166
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.1090263940
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2061622714
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.1280779669
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.4257058755
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.67063316
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1379815236
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.886763463
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.2931154386
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1606628547
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.3013925772
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.162930645
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.2456855015
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.2962949653
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.254551701
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.670439225
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.2847618682
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.284059508
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.4168811202
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.2366422846
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.336926099
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.930072770
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.2310595807
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1234401863
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2785760928
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1962080187
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/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2549082167
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/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.3224017482
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/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.3319695470
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.1916027682
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.3906403890
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.2747269682
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.1756700244
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/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.622421179
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1590729426
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/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.3184207108
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.2462628902
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.3466147149
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.1674720927
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.92715544
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.2150584371
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.67025151
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.3309243304
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.3666770660
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.3138221547
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.143329567
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2144896672
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1728482756
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2761594924
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/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3484359040
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.2558461231
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.1952952197
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.3188299823
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.2901385382
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.2543129487
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.122684017
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.769426032
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3784853684
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1288993901
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1620863404
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1527364744
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.2531636185
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.1823741574
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.1153197129
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.336077232
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.257755960



Total test records in report: 1107
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.1623156535 Sep 04 02:26:25 AM UTC 24 Sep 04 02:26:27 AM UTC 24 29686829 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.1628867176 Sep 04 02:26:27 AM UTC 24 Sep 04 02:26:28 AM UTC 24 31476022 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.3841921288 Sep 04 02:26:26 AM UTC 24 Sep 04 02:26:29 AM UTC 24 83176796 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.2257112966 Sep 04 02:26:27 AM UTC 24 Sep 04 02:26:29 AM UTC 24 177323818 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.2052479132 Sep 04 02:26:27 AM UTC 24 Sep 04 02:26:29 AM UTC 24 64147076 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.1393953193 Sep 04 02:26:27 AM UTC 24 Sep 04 02:26:29 AM UTC 24 55540659 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2084290065 Sep 04 02:26:27 AM UTC 24 Sep 04 02:26:29 AM UTC 24 52521561 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.3458225267 Sep 04 02:26:27 AM UTC 24 Sep 04 02:26:29 AM UTC 24 163557128 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.3189469244 Sep 04 02:26:38 AM UTC 24 Sep 04 02:26:46 AM UTC 24 1141293529 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.2756606829 Sep 04 02:26:28 AM UTC 24 Sep 04 02:26:30 AM UTC 24 113461740 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.1139294278 Sep 04 02:26:28 AM UTC 24 Sep 04 02:26:30 AM UTC 24 72846078 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.3983002005 Sep 04 02:26:28 AM UTC 24 Sep 04 02:26:30 AM UTC 24 291292309 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.1666612745 Sep 04 02:26:28 AM UTC 24 Sep 04 02:26:30 AM UTC 24 51056187 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.1350040683 Sep 04 02:26:28 AM UTC 24 Sep 04 02:26:30 AM UTC 24 52444603 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.3350134146 Sep 04 02:26:28 AM UTC 24 Sep 04 02:26:30 AM UTC 24 176472309 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3896178560 Sep 04 02:26:27 AM UTC 24 Sep 04 02:26:30 AM UTC 24 1069348863 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.3930191464 Sep 04 02:26:28 AM UTC 24 Sep 04 02:26:30 AM UTC 24 125061162 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2821404805 Sep 04 02:26:27 AM UTC 24 Sep 04 02:26:31 AM UTC 24 797176877 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.1713384561 Sep 04 02:26:29 AM UTC 24 Sep 04 02:26:31 AM UTC 24 36799717 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.2400840505 Sep 04 02:26:30 AM UTC 24 Sep 04 02:26:31 AM UTC 24 86294000 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.3273787939 Sep 04 02:26:29 AM UTC 24 Sep 04 02:26:31 AM UTC 24 48390856 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.4241591569 Sep 04 02:26:29 AM UTC 24 Sep 04 02:26:31 AM UTC 24 175234353 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2426670786 Sep 04 02:26:30 AM UTC 24 Sep 04 02:26:31 AM UTC 24 120887765 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.1743583899 Sep 04 02:26:29 AM UTC 24 Sep 04 02:26:32 AM UTC 24 356306854 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.212415254 Sep 04 02:26:30 AM UTC 24 Sep 04 02:26:32 AM UTC 24 139307046 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.1294337670 Sep 04 02:26:30 AM UTC 24 Sep 04 02:26:32 AM UTC 24 260709120 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1544811460 Sep 04 02:26:31 AM UTC 24 Sep 04 02:26:33 AM UTC 24 32247269 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.3197586890 Sep 04 02:26:31 AM UTC 24 Sep 04 02:26:33 AM UTC 24 92578755 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.1327567663 Sep 04 02:26:31 AM UTC 24 Sep 04 02:26:33 AM UTC 24 384977780 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.3037632728 Sep 04 02:26:31 AM UTC 24 Sep 04 02:26:33 AM UTC 24 55933108 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.3570197870 Sep 04 02:26:31 AM UTC 24 Sep 04 02:26:33 AM UTC 24 237655042 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.584944399 Sep 04 02:26:31 AM UTC 24 Sep 04 02:26:33 AM UTC 24 63367382 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.317853480 Sep 04 02:26:31 AM UTC 24 Sep 04 02:26:33 AM UTC 24 244081798 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.3263862502 Sep 04 02:26:31 AM UTC 24 Sep 04 02:26:33 AM UTC 24 52562386 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.3593569570 Sep 04 02:26:31 AM UTC 24 Sep 04 02:26:33 AM UTC 24 29401617 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.1761952481 Sep 04 02:26:31 AM UTC 24 Sep 04 02:26:33 AM UTC 24 141468625 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2806225166 Sep 04 02:26:30 AM UTC 24 Sep 04 02:26:33 AM UTC 24 823101734 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.100926357 Sep 04 02:26:31 AM UTC 24 Sep 04 02:26:33 AM UTC 24 278981592 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.2548848439 Sep 04 02:26:32 AM UTC 24 Sep 04 02:26:33 AM UTC 24 80631963 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.3007579589 Sep 04 02:26:32 AM UTC 24 Sep 04 02:26:34 AM UTC 24 277225954 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.1351921171 Sep 04 02:26:31 AM UTC 24 Sep 04 02:26:34 AM UTC 24 94358917 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.2979840701 Sep 04 02:26:31 AM UTC 24 Sep 04 02:26:34 AM UTC 24 341304312 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.585972755 Sep 04 02:26:31 AM UTC 24 Sep 04 02:26:34 AM UTC 24 240134290 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.261585697 Sep 04 02:26:29 AM UTC 24 Sep 04 02:26:34 AM UTC 24 1578934666 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4222525722 Sep 04 02:26:30 AM UTC 24 Sep 04 02:26:34 AM UTC 24 884179003 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.3861872117 Sep 04 02:26:33 AM UTC 24 Sep 04 02:26:35 AM UTC 24 43285718 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.3319861505 Sep 04 02:26:33 AM UTC 24 Sep 04 02:26:35 AM UTC 24 32219499 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.3760948182 Sep 04 02:26:33 AM UTC 24 Sep 04 02:26:35 AM UTC 24 24829288 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3075052964 Sep 04 02:26:32 AM UTC 24 Sep 04 02:26:35 AM UTC 24 1813776616 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1636409219 Sep 04 02:26:33 AM UTC 24 Sep 04 02:26:35 AM UTC 24 53524478 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.2663550699 Sep 04 02:26:40 AM UTC 24 Sep 04 02:26:44 AM UTC 24 59508590 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.3589232383 Sep 04 02:26:33 AM UTC 24 Sep 04 02:26:35 AM UTC 24 143483165 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.167450855 Sep 04 02:26:33 AM UTC 24 Sep 04 02:26:35 AM UTC 24 94733133 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.310589138 Sep 04 02:26:33 AM UTC 24 Sep 04 02:26:35 AM UTC 24 727994131 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.98978795 Sep 04 02:26:33 AM UTC 24 Sep 04 02:26:35 AM UTC 24 573823543 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.2863278830 Sep 04 02:26:33 AM UTC 24 Sep 04 02:26:35 AM UTC 24 147702471 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.1828324233 Sep 04 02:26:33 AM UTC 24 Sep 04 02:26:35 AM UTC 24 31409931 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.1325611536 Sep 04 02:26:33 AM UTC 24 Sep 04 02:26:35 AM UTC 24 35804446 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.2018197161 Sep 04 02:26:33 AM UTC 24 Sep 04 02:26:36 AM UTC 24 933634112 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2553372795 Sep 04 02:26:33 AM UTC 24 Sep 04 02:26:36 AM UTC 24 1355217287 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.2008592329 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:38 AM UTC 24 256556511 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.4135337738 Sep 04 02:26:33 AM UTC 24 Sep 04 02:26:38 AM UTC 24 5357228628 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.3346357342 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:38 AM UTC 24 36401022 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.475728544 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:38 AM UTC 24 263707350 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.1726941170 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:38 AM UTC 24 194539181 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.47898131 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:40 AM UTC 24 840101452 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.755150981 Sep 04 02:26:31 AM UTC 24 Sep 04 02:26:40 AM UTC 24 2732085618 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.1582795582 Sep 04 02:26:29 AM UTC 24 Sep 04 02:26:41 AM UTC 24 7906961060 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3144305614 Sep 04 02:26:41 AM UTC 24 Sep 04 02:26:43 AM UTC 24 66320189 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.1078733993 Sep 04 02:26:38 AM UTC 24 Sep 04 02:26:43 AM UTC 24 33200267 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.119349174 Sep 04 02:26:38 AM UTC 24 Sep 04 02:26:43 AM UTC 24 615233008 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.745373334 Sep 04 02:26:38 AM UTC 24 Sep 04 02:26:43 AM UTC 24 58559158 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.2877338232 Sep 04 02:26:39 AM UTC 24 Sep 04 02:26:43 AM UTC 24 125632764 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.807648275 Sep 04 02:26:42 AM UTC 24 Sep 04 02:26:43 AM UTC 24 31178104 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.4064956294 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:44 AM UTC 24 26133467 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.2327948457 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:44 AM UTC 24 29511804 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.3731366059 Sep 04 02:26:40 AM UTC 24 Sep 04 02:26:44 AM UTC 24 65560107 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.962058981 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:45 AM UTC 24 40505435 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.754874486 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:45 AM UTC 24 2278176604 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.3149833198 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:45 AM UTC 24 33418562 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.1780773007 Sep 04 02:26:43 AM UTC 24 Sep 04 02:26:45 AM UTC 24 409838305 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.4247489618 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:45 AM UTC 24 29805148 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2956667701 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:45 AM UTC 24 64724101 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2549082167 Sep 04 02:26:40 AM UTC 24 Sep 04 02:26:46 AM UTC 24 1166240688 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3547772087 Sep 04 02:26:41 AM UTC 24 Sep 04 02:26:46 AM UTC 24 817977306 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.1644684741 Sep 04 02:26:46 AM UTC 24 Sep 04 02:26:48 AM UTC 24 55888022 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.1064880942 Sep 04 02:26:46 AM UTC 24 Sep 04 02:26:48 AM UTC 24 262562852 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.2672828423 Sep 04 02:26:46 AM UTC 24 Sep 04 02:26:48 AM UTC 24 35534515 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.1638780917 Sep 04 02:26:46 AM UTC 24 Sep 04 02:26:48 AM UTC 24 184356598 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.4202629694 Sep 04 02:26:46 AM UTC 24 Sep 04 02:26:48 AM UTC 24 202528773 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.1537194599 Sep 04 02:26:33 AM UTC 24 Sep 04 02:26:49 AM UTC 24 4568716224 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3765574940 Sep 04 02:26:46 AM UTC 24 Sep 04 02:26:50 AM UTC 24 799861908 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.2759317422 Sep 04 02:26:46 AM UTC 24 Sep 04 02:26:51 AM UTC 24 956124770 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.1841555972 Sep 04 02:26:37 AM UTC 24 Sep 04 02:26:53 AM UTC 24 46826559 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.2617538078 Sep 04 02:26:37 AM UTC 24 Sep 04 02:26:53 AM UTC 24 111572527 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.3086070479 Sep 04 02:26:38 AM UTC 24 Sep 04 02:26:54 AM UTC 24 9781246144 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.1670952103 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:58 AM UTC 24 45156888 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.1645534353 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:58 AM UTC 24 68610873 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.4237014050 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:58 AM UTC 24 43238404 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.1771288089 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:58 AM UTC 24 397277140 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.3913031573 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:58 AM UTC 24 114068732 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.4098351655 Sep 04 02:26:35 AM UTC 24 Sep 04 02:26:59 AM UTC 24 916648436 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.3893273101 Sep 04 02:26:35 AM UTC 24 Sep 04 02:27:01 AM UTC 24 1464145828 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.4046819790 Sep 04 02:26:35 AM UTC 24 Sep 04 02:27:01 AM UTC 24 2581479585 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.355751785 Sep 04 02:26:54 AM UTC 24 Sep 04 02:27:03 AM UTC 24 42822579 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.938451325 Sep 04 02:26:54 AM UTC 24 Sep 04 02:27:03 AM UTC 24 28086366 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.1952952197 Sep 04 02:27:15 AM UTC 24 Sep 04 02:27:18 AM UTC 24 45573947 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.3272190575 Sep 04 02:26:44 AM UTC 24 Sep 04 02:27:03 AM UTC 24 58748181 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.4035464381 Sep 04 02:26:44 AM UTC 24 Sep 04 02:27:03 AM UTC 24 51081372 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.2203516261 Sep 04 02:26:48 AM UTC 24 Sep 04 02:27:03 AM UTC 24 38582355 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.2463491003 Sep 04 02:26:48 AM UTC 24 Sep 04 02:27:03 AM UTC 24 547824049 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.3129351545 Sep 04 02:26:44 AM UTC 24 Sep 04 02:27:03 AM UTC 24 64595224 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.3339506453 Sep 04 02:26:48 AM UTC 24 Sep 04 02:27:03 AM UTC 24 62078916 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.3899892208 Sep 04 02:26:48 AM UTC 24 Sep 04 02:27:03 AM UTC 24 166498305 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.2532707712 Sep 04 02:26:48 AM UTC 24 Sep 04 02:27:03 AM UTC 24 145876411 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.2428410814 Sep 04 02:26:48 AM UTC 24 Sep 04 02:27:03 AM UTC 24 87855752 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.3932219324 Sep 04 02:26:44 AM UTC 24 Sep 04 02:27:03 AM UTC 24 209447914 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.1058949051 Sep 04 02:26:44 AM UTC 24 Sep 04 02:27:03 AM UTC 24 121383460 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1269177387 Sep 04 02:26:54 AM UTC 24 Sep 04 02:27:03 AM UTC 24 278375213 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.1756700244 Sep 04 02:27:05 AM UTC 24 Sep 04 02:27:07 AM UTC 24 44395974 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.240906438 Sep 04 02:27:05 AM UTC 24 Sep 04 02:27:07 AM UTC 24 29174563 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.3666770660 Sep 04 02:27:05 AM UTC 24 Sep 04 02:27:08 AM UTC 24 66267718 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.3184207108 Sep 04 02:27:05 AM UTC 24 Sep 04 02:27:08 AM UTC 24 88134330 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.3309243304 Sep 04 02:27:05 AM UTC 24 Sep 04 02:27:08 AM UTC 24 69440356 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.3271544202 Sep 04 02:27:05 AM UTC 24 Sep 04 02:27:08 AM UTC 24 106596152 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.2040957250 Sep 04 02:27:05 AM UTC 24 Sep 04 02:27:08 AM UTC 24 221589964 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.856305292 Sep 04 02:27:05 AM UTC 24 Sep 04 02:27:10 AM UTC 24 2383289546 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.2531636185 Sep 04 02:27:11 AM UTC 24 Sep 04 02:27:12 AM UTC 24 27089879 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.122684017 Sep 04 02:27:11 AM UTC 24 Sep 04 02:27:13 AM UTC 24 67456012 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.2543129487 Sep 04 02:27:11 AM UTC 24 Sep 04 02:27:13 AM UTC 24 192967537 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.3466147149 Sep 04 02:27:08 AM UTC 24 Sep 04 02:27:13 AM UTC 24 31219713 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.2150584371 Sep 04 02:27:09 AM UTC 24 Sep 04 02:27:13 AM UTC 24 54538440 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.3298113992 Sep 04 02:27:20 AM UTC 24 Sep 04 02:27:23 AM UTC 24 50499440 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.143329567 Sep 04 02:27:08 AM UTC 24 Sep 04 02:27:13 AM UTC 24 204236790 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.3138221547 Sep 04 02:27:09 AM UTC 24 Sep 04 02:27:13 AM UTC 24 144732697 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.92715544 Sep 04 02:27:09 AM UTC 24 Sep 04 02:27:13 AM UTC 24 50920257 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.2462628902 Sep 04 02:27:09 AM UTC 24 Sep 04 02:27:13 AM UTC 24 150999696 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.2747269682 Sep 04 02:27:02 AM UTC 24 Sep 04 02:27:13 AM UTC 24 53376686 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.1674720927 Sep 04 02:27:09 AM UTC 24 Sep 04 02:27:13 AM UTC 24 109013479 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.3906403890 Sep 04 02:27:05 AM UTC 24 Sep 04 02:27:13 AM UTC 24 46111209 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.622421179 Sep 04 02:27:01 AM UTC 24 Sep 04 02:27:13 AM UTC 24 82706333 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.1206044073 Sep 04 02:27:05 AM UTC 24 Sep 04 02:27:13 AM UTC 24 72100082 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.1064579550 Sep 04 02:27:05 AM UTC 24 Sep 04 02:27:14 AM UTC 24 170292325 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.1916027682 Sep 04 02:27:02 AM UTC 24 Sep 04 02:27:14 AM UTC 24 384600914 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.3224017482 Sep 04 02:27:00 AM UTC 24 Sep 04 02:27:14 AM UTC 24 34284577 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.1688107365 Sep 04 02:26:59 AM UTC 24 Sep 04 02:27:15 AM UTC 24 281144043 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3898075607 Sep 04 02:27:00 AM UTC 24 Sep 04 02:27:16 AM UTC 24 1276544840 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1590729426 Sep 04 02:27:00 AM UTC 24 Sep 04 02:27:16 AM UTC 24 802985903 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.507321110 Sep 04 02:26:52 AM UTC 24 Sep 04 02:27:16 AM UTC 24 968029852 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.3925933478 Sep 04 02:27:11 AM UTC 24 Sep 04 02:27:17 AM UTC 24 2506214874 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.3319695470 Sep 04 02:27:00 AM UTC 24 Sep 04 02:27:18 AM UTC 24 29846880 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.2317117111 Sep 04 02:27:00 AM UTC 24 Sep 04 02:27:18 AM UTC 24 196469787 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3484359040 Sep 04 02:27:15 AM UTC 24 Sep 04 02:27:18 AM UTC 24 31548311 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.3188299823 Sep 04 02:27:15 AM UTC 24 Sep 04 02:27:18 AM UTC 24 47344812 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1527364744 Sep 04 02:27:15 AM UTC 24 Sep 04 02:27:18 AM UTC 24 64278840 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.67025151 Sep 04 02:27:10 AM UTC 24 Sep 04 02:27:18 AM UTC 24 84423928 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.2901385382 Sep 04 02:27:15 AM UTC 24 Sep 04 02:27:18 AM UTC 24 57229503 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3784853684 Sep 04 02:27:15 AM UTC 24 Sep 04 02:27:18 AM UTC 24 204718225 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2761594924 Sep 04 02:27:06 AM UTC 24 Sep 04 02:27:18 AM UTC 24 103919864 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.3272208452 Sep 04 02:27:15 AM UTC 24 Sep 04 02:27:18 AM UTC 24 326075648 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.2558461231 Sep 04 02:27:15 AM UTC 24 Sep 04 02:27:18 AM UTC 24 114013151 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.769426032 Sep 04 02:27:15 AM UTC 24 Sep 04 02:27:18 AM UTC 24 115678998 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.2174975677 Sep 04 02:26:51 AM UTC 24 Sep 04 02:27:19 AM UTC 24 2296264067 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1288993901 Sep 04 02:27:15 AM UTC 24 Sep 04 02:27:19 AM UTC 24 1188544863 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.1376043856 Sep 04 02:27:05 AM UTC 24 Sep 04 02:27:19 AM UTC 24 39918716929 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1620863404 Sep 04 02:27:15 AM UTC 24 Sep 04 02:27:20 AM UTC 24 805241741 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2144896672 Sep 04 02:27:05 AM UTC 24 Sep 04 02:27:20 AM UTC 24 907445806 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1728482756 Sep 04 02:27:05 AM UTC 24 Sep 04 02:27:20 AM UTC 24 857811388 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1880791859 Sep 04 02:27:20 AM UTC 24 Sep 04 02:27:22 AM UTC 24 36343551 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.2948773641 Sep 04 02:27:20 AM UTC 24 Sep 04 02:27:22 AM UTC 24 46777203 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.4206939277 Sep 04 02:27:20 AM UTC 24 Sep 04 02:27:23 AM UTC 24 58753369 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.4160383798 Sep 04 02:27:18 AM UTC 24 Sep 04 02:27:23 AM UTC 24 22469569 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.4082603514 Sep 04 02:27:20 AM UTC 24 Sep 04 02:27:23 AM UTC 24 53504272 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.846989303 Sep 04 02:27:20 AM UTC 24 Sep 04 02:27:23 AM UTC 24 51660012 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.2288924887 Sep 04 02:27:18 AM UTC 24 Sep 04 02:27:23 AM UTC 24 289666575 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.2824358243 Sep 04 02:27:20 AM UTC 24 Sep 04 02:27:23 AM UTC 24 1873759083 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.3792485999 Sep 04 02:27:20 AM UTC 24 Sep 04 02:27:23 AM UTC 24 59304639 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.3181467578 Sep 04 02:27:18 AM UTC 24 Sep 04 02:27:23 AM UTC 24 140017406 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.1272061982 Sep 04 02:27:20 AM UTC 24 Sep 04 02:27:23 AM UTC 24 150543245 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.3804980163 Sep 04 02:27:20 AM UTC 24 Sep 04 02:27:23 AM UTC 24 29432872 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.3176660458 Sep 04 02:27:20 AM UTC 24 Sep 04 02:27:23 AM UTC 24 156601228 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.190591912 Sep 04 02:27:21 AM UTC 24 Sep 04 02:27:23 AM UTC 24 171212178 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.1309380348 Sep 04 02:27:21 AM UTC 24 Sep 04 02:27:23 AM UTC 24 282823563 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.4264020350 Sep 04 02:27:21 AM UTC 24 Sep 04 02:27:23 AM UTC 24 67253319 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.1035883718 Sep 04 02:27:21 AM UTC 24 Sep 04 02:27:23 AM UTC 24 260631826 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.2368086697 Sep 04 02:27:10 AM UTC 24 Sep 04 02:27:24 AM UTC 24 9737964054 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.4229245596 Sep 04 02:27:20 AM UTC 24 Sep 04 02:27:26 AM UTC 24 2209732720 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.2664887820 Sep 04 02:27:20 AM UTC 24 Sep 04 02:27:27 AM UTC 24 3118372319 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.4220665113 Sep 04 02:27:25 AM UTC 24 Sep 04 02:27:28 AM UTC 24 69247380 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.2642831042 Sep 04 02:27:25 AM UTC 24 Sep 04 02:27:28 AM UTC 24 29621915 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.2033446583 Sep 04 02:27:29 AM UTC 24 Sep 04 02:27:38 AM UTC 24 46040807 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.1729927301 Sep 04 02:27:25 AM UTC 24 Sep 04 02:27:28 AM UTC 24 44534617 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.2654854862 Sep 04 02:27:25 AM UTC 24 Sep 04 02:27:28 AM UTC 24 182924975 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.2499846615 Sep 04 02:27:25 AM UTC 24 Sep 04 02:27:28 AM UTC 24 174686994 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.1261731760 Sep 04 02:27:29 AM UTC 24 Sep 04 02:27:39 AM UTC 24 29177439 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.3695400319 Sep 04 02:27:25 AM UTC 24 Sep 04 02:27:28 AM UTC 24 34791371 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.2123889017 Sep 04 02:27:13 AM UTC 24 Sep 04 02:27:28 AM UTC 24 69710756 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.2227889976 Sep 04 02:27:16 AM UTC 24 Sep 04 02:27:28 AM UTC 24 32924018 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.3365697836 Sep 04 02:27:25 AM UTC 24 Sep 04 02:27:28 AM UTC 24 313896792 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.336077232 Sep 04 02:27:13 AM UTC 24 Sep 04 02:27:28 AM UTC 24 426713520 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.3085362057 Sep 04 02:27:16 AM UTC 24 Sep 04 02:27:28 AM UTC 24 53441379 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.257755960 Sep 04 02:27:13 AM UTC 24 Sep 04 02:27:28 AM UTC 24 249297552 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3371914343 Sep 04 02:27:26 AM UTC 24 Sep 04 02:27:28 AM UTC 24 68551672 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.1086825561 Sep 04 02:27:17 AM UTC 24 Sep 04 02:27:28 AM UTC 24 196223106 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.3186308371 Sep 04 02:27:25 AM UTC 24 Sep 04 02:27:28 AM UTC 24 302000614 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.385578311 Sep 04 02:27:23 AM UTC 24 Sep 04 02:27:29 AM UTC 24 1251599943 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1343386288 Sep 04 02:27:23 AM UTC 24 Sep 04 02:27:29 AM UTC 24 929507216 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4142445245 Sep 04 02:27:25 AM UTC 24 Sep 04 02:27:29 AM UTC 24 960328921 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3779477381 Sep 04 02:27:26 AM UTC 24 Sep 04 02:27:30 AM UTC 24 1066230160 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.1823741574 Sep 04 02:27:15 AM UTC 24 Sep 04 02:27:31 AM UTC 24 2958394617 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup_reset.3603507274 Sep 04 02:27:31 AM UTC 24 Sep 04 02:27:33 AM UTC 24 35071560 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_aborted_low_power.906828853 Sep 04 02:27:31 AM UTC 24 Sep 04 02:27:33 AM UTC 24 77028783 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.4012628283 Sep 04 02:27:31 AM UTC 24 Sep 04 02:27:33 AM UTC 24 39706891 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_global_esc.255521546 Sep 04 02:27:31 AM UTC 24 Sep 04 02:27:33 AM UTC 24 87474516 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.599872316 Sep 04 02:27:31 AM UTC 24 Sep 04 02:27:33 AM UTC 24 167347131 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup.2859346764 Sep 04 02:27:31 AM UTC 24 Sep 04 02:27:33 AM UTC 24 328072785 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_glitch.3828654287 Sep 04 02:27:31 AM UTC 24 Sep 04 02:27:33 AM UTC 24 46454787 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_escalation_timeout.4183834870 Sep 04 02:27:31 AM UTC 24 Sep 04 02:27:33 AM UTC 24 110343632 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.3216749897 Sep 04 02:27:31 AM UTC 24 Sep 04 02:27:33 AM UTC 24 318795593 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.179083986 Sep 04 02:27:31 AM UTC 24 Sep 04 02:27:35 AM UTC 24 750218366 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1824337372 Sep 04 02:27:31 AM UTC 24 Sep 04 02:27:35 AM UTC 24 950801308 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all_with_rand_reset.1744571426 Sep 04 02:27:25 AM UTC 24 Sep 04 02:27:38 AM UTC 24 5256551014 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1491862622 Sep 04 02:27:29 AM UTC 24 Sep 04 02:27:38 AM UTC 24 29310735 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.3762894463 Sep 04 02:27:29 AM UTC 24 Sep 04 02:27:38 AM UTC 24 81712609 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.3982964775 Sep 04 02:27:25 AM UTC 24 Sep 04 02:27:38 AM UTC 24 97376086 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.16663371 Sep 04 02:27:29 AM UTC 24 Sep 04 02:27:38 AM UTC 24 39354385 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.1841716828 Sep 04 02:27:29 AM UTC 24 Sep 04 02:27:38 AM UTC 24 162754691 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup_reset.751335101 Sep 04 02:27:35 AM UTC 24 Sep 04 02:27:38 AM UTC 24 122439489 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.2223507144 Sep 04 02:27:29 AM UTC 24 Sep 04 02:27:38 AM UTC 24 107883174 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.2825612776 Sep 04 02:27:29 AM UTC 24 Sep 04 02:27:39 AM UTC 24 91737487 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_aborted_low_power.746736612 Sep 04 02:27:36 AM UTC 24 Sep 04 02:27:38 AM UTC 24 55417710 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.2643708622 Sep 04 02:27:29 AM UTC 24 Sep 04 02:27:38 AM UTC 24 157831709 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.498466462 Sep 04 02:27:29 AM UTC 24 Sep 04 02:27:38 AM UTC 24 61980866 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.4138307741 Sep 04 02:27:29 AM UTC 24 Sep 04 02:27:39 AM UTC 24 174513892 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all.495699443 Sep 04 02:27:29 AM UTC 24 Sep 04 02:27:40 AM UTC 24 774305380 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3660347250 Sep 04 02:27:36 AM UTC 24 Sep 04 02:27:40 AM UTC 24 811303219 ps
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T174 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.3176411783 Sep 04 02:26:37 AM UTC 24 Sep 04 02:27:42 AM UTC 24 65711177 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.958961876 Sep 04 02:26:37 AM UTC 24 Sep 04 02:27:43 AM UTC 24 156804362 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.3793704490 Sep 04 02:26:37 AM UTC 24 Sep 04 02:27:43 AM UTC 24 432592133 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_smoke.2308187948 Sep 04 02:27:49 AM UTC 24 Sep 04 02:27:51 AM UTC 24 32205568 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.690639411 Sep 04 02:26:57 AM UTC 24 Sep 04 02:27:43 AM UTC 24 272064333 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_disable_rom_integrity_check.2077327275 Sep 04 02:27:40 AM UTC 24 Sep 04 02:27:43 AM UTC 24 87473071 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_invalid.2823114428 Sep 04 02:27:40 AM UTC 24 Sep 04 02:27:43 AM UTC 24 80247516 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_smoke.2729495595 Sep 04 02:27:40 AM UTC 24 Sep 04 02:27:43 AM UTC 24 37710739 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_glitch.2044778626 Sep 04 02:27:40 AM UTC 24 Sep 04 02:27:43 AM UTC 24 47057635 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset_invalid.2098005409 Sep 04 02:27:40 AM UTC 24 Sep 04 02:27:43 AM UTC 24 162503607 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.1361577428 Sep 04 02:27:40 AM UTC 24 Sep 04 02:27:43 AM UTC 24 39054595 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all.38533672 Sep 04 02:27:45 AM UTC 24 Sep 04 02:27:49 AM UTC 24 698348412 ps
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