Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::esc_reset_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::esc_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

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Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::esc_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	3	0	3	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::esc_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_reset_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::esc_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
reset_cross	3	0	3	100.00	100	1	1	0

Summary for Variable esc_reset_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_reset_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30857

1

T1

2

T2

1

T3

8

auto[1]

2772

1

T3

7

T6

1

T13

5

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Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14013

1

T1

1

T3

15

T6

1

auto[1]

19616

1

T1

1

T2

1

T4

11

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Summary for Cross reset_cross

Samples crossed: esc_reset_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	3	0	3	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for reset_cross

Bins

esc_reset_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

11241

1

T1

1

T3

8

T7

1

auto[0]

auto[1]

19616

1

T1

1

T2

1

T4

11

auto[1]

auto[0]

2772

1

T3

7

T6

1

T13

5

User Defined Cross Bins for reset_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal	0	Illegal