Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24211

1

T1

2

T3

16

T4

20

auto[1]

23226

1

T3

14

T4

12

T5

18

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24348

1

T1

2

T3

16

T4

12

auto[1]

23089

1

T3

14

T4

20

T5

22

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23142

1

T3

12

T4

30

T5

22

auto[1]

24295

1

T1

2

T3

18

T4

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26697

1

T1

1

T3

15

T4

16

auto[1]

20740

1

T1

1

T3

15

T4

16

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23172

1

T3

12

T4

22

T5

22

auto[1]

24265

1

T1

2

T3

18

T4

10

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24330

1

T1

2

T3

16

T4

12

auto[1]

23107

1

T3

14

T4

20

T5

22

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

862

1

T4

1

T14

1

T15

5

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

685

1

T4

1

T14

1

T15

5

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

817

1

T3

1

T14

4

T34

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

648

1

T3

1

T14

4

T34

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

830

1

T40

1

T14

2

T15

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

634

1

T14

2

T15

2

T33

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1285

1

T1

1

T3

1

T40

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1086

1

T1

1

T3

1

T14

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

795

1

T3

1

T4

2

T40

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

628

1

T3

1

T4

2

T14

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

818

1

T5

1

T6

1

T40

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

629

1

T5

1

T40

1

T14

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

819

1

T4

2

T40

1

T14

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

625

1

T4

2

T40

1

T14

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

829

1

T3

1

T5

2

T40

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

648

1

T3

1

T5

2

T40

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

843

1

T4

2

T5

2

T40

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

649

1

T4

2

T5

2

T40

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

793

1

T40

2

T15

2

T38

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

612

1

T40

2

T15

2

T38

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

825

1

T14

2

T15

2

T45

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

632

1

T14

2

T15

2

T33

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

851

1

T3

2

T40

2

T14

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

668

1

T3

2

T40

1

T14

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

803

1

T3

1

T4

2

T5

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

622

1

T3

1

T4

2

T5

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

830

1

T5

1

T14

1

T15

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

649

1

T5

1

T14

1

T15

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

777

1

T5

1

T14

1

T15

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

609

1

T5

1

T14

1

T15

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

804

1

T3

1

T4

1

T40

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

606

1

T3

1

T4

1

T40

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

792

1

T3

1

T5

1

T40

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

614

1

T3

1

T5

1

T40

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

840

1

T5

1

T14

2

T33

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

642

1

T5

1

T14

2

T33

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

805

1

T5

1

T40

1

T14

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

637

1

T5

1

T14

3

T33

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

859

1

T3

1

T5

1

T14

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

659

1

T3

1

T5

1

T14

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

796

1

T3

1

T4

1

T14

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

648

1

T3

1

T4

1

T14

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

807

1

T40

1

T14

3

T15

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

623

1

T14

3

T15

2

T34

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

842

1

T3

1

T14

1

T15

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

663

1

T3

1

T14

1

T15

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

842

1

T14

1

T15

1

T36

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

641

1

T14

1

T15

1

T36

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

810

1

T4

3

T5

1

T40

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

631

1

T4

3

T5

1

T14

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

838

1

T33

2

T16

1

T38

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

630

1

T33

2

T38

3

T17

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

828

1

T3

1

T14

2

T15

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

648

1

T3

1

T14

2

T15

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

785

1

T3

1

T14

2

T15

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

592

1

T3

1

T14

2

T15

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

781

1

T5

1

T14

3

T15

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

594

1

T5

1

T14

3

T15

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

830

1

T3

1

T5

1

T40

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

613

1

T3

1

T5

1

T14

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

794

1

T4

2

T5

2

T15

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

621

1

T4

2

T5

2

T15

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

867

1

T40

1

T15

1

T33

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

654

1

T40

1

T15

1

T33

1