Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20787

1

T1

4

T2

2

T4

12

auto[1]

19984

1

T1

7

T4

14

T5

9

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20760

1

T1

5

T2

2

T4

10

auto[1]

20011

1

T1

6

T4

16

T5

7

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20191

1

T1

5

T4

14

T5

5

auto[1]

20580

1

T1

6

T2

2

T4

12

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22737

1

T1

8

T2

1

T4

13

auto[1]

18034

1

T1

3

T2

1

T4

13

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20054

1

T1

7

T4

12

T5

8

auto[1]

20717

1

T1

4

T2

2

T4

14

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20715

1

T1

4

T2

2

T4

16

auto[1]

20056

1

T1

7

T4

10

T5

9

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

655

1

T7

1

T43

1

T32

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

502

1

T7

1

T43

1

T32

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

733

1

T6

1

T7

1

T37

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

567

1

T6

1

T7

1

T37

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

668

1

T43

2

T16

2

T18

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

519

1

T43

2

T16

2

T28

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1087

1

T2

1

T4

1

T5

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

956

1

T2

1

T4

1

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

698

1

T5

1

T7

1

T16

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

573

1

T7

1

T16

2

T32

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

646

1

T16

1

T32

2

T35

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

502

1

T16

1

T32

2

T35

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

753

1

T1

1

T4

2

T6

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

616

1

T4

2

T6

1

T43

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

676

1

T6

1

T16

1

T32

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

520

1

T6

1

T16

1

T32

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

716

1

T7

1

T43

6

T16

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

590

1

T7

1

T43

4

T16

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

725

1

T1

1

T43

1

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

565

1

T32

1

T18

2

T60

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

692

1

T4

1

T5

1

T6

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

546

1

T4

1

T6

1

T7

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

667

1

T6

1

T16

1

T32

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

533

1

T6

1

T16

1

T32

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

715

1

T1

1

T6

1

T7

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

559

1

T6

1

T7

1

T43

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

727

1

T4

1

T5

1

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

545

1

T4

1

T6

1

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

735

1

T1

1

T6

2

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

584

1

T6

2

T7

1

T16

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

690

1

T4

1

T6

1

T43

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

527

1

T4

1

T6

1

T43

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

677

1

T6

3

T16

1

T31

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

542

1

T6

3

T16

1

T31

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

649

1

T1

1

T4

1

T6

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

532

1

T1

1

T4

1

T6

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

719

1

T4

1

T7

2

T43

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

575

1

T4

1

T7

2

T16

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

696

1

T5

1

T6

1

T7

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

549

1

T6

1

T7

2

T16

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

703

1

T41

1

T16

3

T60

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

554

1

T41

1

T16

3

T76

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

708

1

T5

3

T16

3

T32

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

558

1

T16

3

T32

1

T34

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

717

1

T1

1

T7

1

T43

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

575

1

T1

1

T7

1

T43

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

744

1

T43

1

T16

4

T32

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

591

1

T43

1

T16

4

T32

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

725

1

T4

2

T7

2

T43

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

592

1

T4

2

T7

2

T43

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

746

1

T1

1

T4

1

T6

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

576

1

T4

1

T6

1

T7

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

677

1

T4

1

T6

1

T41

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

553

1

T4

1

T6

1

T16

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

674

1

T5

1

T6

1

T43

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

512

1

T6

1

T43

1

T16

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

707

1

T5

2

T6

1

T43

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

558

1

T6

1

T43

4

T16

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

673

1

T1

1

T4

1

T5

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

536

1

T1

1

T4

1

T7

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

674

1

T5

1

T7

1

T43

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

522

1

T7

1

T43

1

T32

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

665

1

T16

2

T32

2

T35

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

505

1

T16

2

T32

2

T35

1