Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 98.23 96.58 99.62 96.00 96.37 100.00 98.85


Total tests in report: 1105
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
75.58 75.58 94.06 94.06 81.88 81.88 79.10 79.10 52.00 52.00 89.12 89.12 88.68 88.68 44.19 44.19 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.3376558972
83.22 7.65 96.06 2.01 85.73 3.85 85.59 6.50 82.00 30.00 92.56 3.44 90.53 1.84 50.08 5.89 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.4110918531
88.05 4.83 96.79 0.72 87.02 1.28 87.57 1.98 86.00 4.00 93.70 1.15 92.63 2.11 72.67 22.59 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.1116579129
90.13 2.07 96.95 0.16 88.16 1.14 96.80 9.23 88.00 2.00 94.47 0.76 93.68 1.05 72.83 0.16 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.1654780225
91.80 1.67 96.95 0.00 88.45 0.29 98.31 1.51 88.00 0.00 94.47 0.00 93.95 0.26 82.49 9.66 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2482735395
93.22 1.42 97.11 0.16 90.58 2.14 99.06 0.75 88.00 0.00 94.66 0.19 95.26 1.32 87.89 5.40 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.3167218691
94.59 1.37 97.83 0.72 93.72 3.14 99.25 0.19 88.00 0.00 95.42 0.76 96.58 1.32 91.33 3.44 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.1774240949
95.78 1.19 97.83 0.00 93.72 0.00 99.25 0.00 96.00 8.00 95.61 0.19 96.58 0.00 91.49 0.16 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.3512121514
96.08 0.30 97.83 0.00 93.87 0.14 99.25 0.00 96.00 0.00 95.61 0.00 96.58 0.00 93.45 1.96 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.3913266010
96.38 0.30 97.83 0.00 93.87 0.00 99.25 0.00 96.00 0.00 95.80 0.19 96.84 0.26 95.09 1.64 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.2207557835
96.65 0.27 97.83 0.00 94.01 0.14 99.25 0.00 96.00 0.00 95.80 0.00 97.11 0.26 96.56 1.47 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.1456364910
96.91 0.26 98.07 0.24 95.44 1.43 99.25 0.00 96.00 0.00 95.80 0.00 97.11 0.00 96.73 0.16 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.392307633
97.15 0.24 98.23 0.16 95.86 0.43 99.25 0.00 96.00 0.00 96.37 0.57 97.63 0.53 96.73 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.1266911894
97.34 0.19 98.23 0.00 95.86 0.00 99.25 0.00 96.00 0.00 96.37 0.00 98.95 1.32 96.73 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.4247288289
97.44 0.10 98.23 0.00 95.86 0.00 99.25 0.00 96.00 0.00 96.37 0.00 99.47 0.53 96.89 0.16 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2290492052
97.52 0.08 98.23 0.00 95.86 0.00 99.62 0.38 96.00 0.00 96.37 0.00 99.47 0.00 97.05 0.16 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.2301794676
97.59 0.07 98.23 0.00 95.86 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 97.55 0.49 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.734433904
97.66 0.07 98.23 0.00 95.86 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.04 0.49 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2093008767
97.70 0.05 98.23 0.00 95.86 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.36 0.33 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.3910328846
97.75 0.04 98.23 0.00 96.15 0.29 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.36 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3412953470
97.78 0.04 98.23 0.00 96.15 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.26 98.36 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.2485289679
97.81 0.02 98.23 0.00 96.15 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.53 0.16 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.1136415683
97.83 0.02 98.23 0.00 96.15 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.69 0.16 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.3207086163
97.85 0.02 98.23 0.00 96.15 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.85 0.16 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_disable_rom_integrity_check.2360432850
97.87 0.02 98.23 0.00 96.29 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.85 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3133701489
97.89 0.02 98.23 0.00 96.43 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.85 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3757626964
97.91 0.02 98.23 0.00 96.58 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.85 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.4071652831

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2157917545
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1969488000
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2705459580
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.1109725075
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.803205663
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3090520064
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.4157459489
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.665513051
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.760996813
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.1922907534
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.2776297334
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.735078113
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.1668683936
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.4034580906
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1986151496
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.3235314535
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1308847180
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.338612064
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.2827613704
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.160462119
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1429039204
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.3309651969
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.737853545
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2434937944
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.254451504
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.2464717241
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2087005166
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.1438370702
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.386656116
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.6368712
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.1340145874
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3358445530
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.1165228426
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1243959374
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.2762046671
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.3514859796
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.1992989280
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.686463721
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.792042555
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2947184825
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3521558744
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3777371141
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.2407727102
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.119217799
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.3027287162
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2374995160
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.847065403
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.353506539
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.3847320956
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3308782989
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.3695420577
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.1128675634
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.2297342052
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.302907239
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.4030193496
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2111773834
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.572505125
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3673878318
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2679710361
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.4065607929
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.2869455769
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2952537316
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.3629118136
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3655622610
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3980612864
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.2357803184
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.307400705
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.232201076
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.2289142435
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.1912837708
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.774229351
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2031328154
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3824947902
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.724309578
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.1408108705
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.2835378699
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3730633464
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.2553116507
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1455280769
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.2894644658
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.432731860
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.1110948856
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.1164540343
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.694852013
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.3855328986
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.1194606162
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.615942881
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.3342848665
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/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.2305346500
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3514450809
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2793420646
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/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.1126110771
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/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.3426012393
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2256932501
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.659534462
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.2020607514
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.2633365423
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/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.3720544259
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.2917321938
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1269975744
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/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.1595791829
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.466091903
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.752667994
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/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.3353265390
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.2954517803
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.127267421
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.463360069
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.969013534
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.2300111402
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.3334859682
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.3995511631
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.3308617896
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.3075858196
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.2104718595
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.3379823987
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.1933786127
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1181194353
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.3183095152
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.3724865834
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.2015170061
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3814957365
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1325245852
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.1721573466
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.2761315427
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.4137162636
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.3928954424
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.999732273
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.3869093878
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.3668718928
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.267256268
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.2794807317
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.1041137656
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.1216805123
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.1308683142
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.1243811001
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.1523865694
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.187737891
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.306633462
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1572799177
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.159424567
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.168444150
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.2860876321
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.401579473
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.3470211701
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.1433927978
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.218608612
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.3848816032
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.911140077
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3215514182
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.805664372
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.1348581635
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.3612324474
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.2108172457
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.3927118551
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.3178802509
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.46908958
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3518647511
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.814905760
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3035301422
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1418262806
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.167978854
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.2348908121
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.1836411353
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.2577632825
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.4222853634



Total test records in report: 1105
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.849665653 Sep 11 05:39:33 AM UTC 24 Sep 11 05:39:35 AM UTC 24 44696749 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.117003843 Sep 11 05:39:21 AM UTC 24 Sep 11 05:39:23 AM UTC 24 56468830 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.2801692567 Sep 11 05:39:21 AM UTC 24 Sep 11 05:39:23 AM UTC 24 338176627 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.576888025 Sep 11 05:39:21 AM UTC 24 Sep 11 05:39:24 AM UTC 24 236434582 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.1146184330 Sep 11 05:39:21 AM UTC 24 Sep 11 05:39:24 AM UTC 24 105228156 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.3376558972 Sep 11 05:39:21 AM UTC 24 Sep 11 05:39:24 AM UTC 24 373773264 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.615949000 Sep 11 05:39:21 AM UTC 24 Sep 11 05:39:24 AM UTC 24 615655621 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.1979799616 Sep 11 05:39:35 AM UTC 24 Sep 11 05:39:37 AM UTC 24 33297174 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.2927439387 Sep 11 05:39:23 AM UTC 24 Sep 11 05:39:25 AM UTC 24 62931603 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.4071652831 Sep 11 05:39:23 AM UTC 24 Sep 11 05:39:25 AM UTC 24 172854195 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.4110918531 Sep 11 05:39:23 AM UTC 24 Sep 11 05:39:25 AM UTC 24 506986283 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.1266911894 Sep 11 05:39:23 AM UTC 24 Sep 11 05:39:25 AM UTC 24 300442487 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.2207557835 Sep 11 05:39:23 AM UTC 24 Sep 11 05:39:25 AM UTC 24 44507970 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.1878944296 Sep 11 05:39:23 AM UTC 24 Sep 11 05:39:25 AM UTC 24 72871488 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.3001490560 Sep 11 05:39:23 AM UTC 24 Sep 11 05:39:25 AM UTC 24 73538274 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.1456364910 Sep 11 05:39:23 AM UTC 24 Sep 11 05:39:25 AM UTC 24 355557745 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3164793456 Sep 11 05:39:21 AM UTC 24 Sep 11 05:39:26 AM UTC 24 745815192 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.494658094 Sep 11 05:39:23 AM UTC 24 Sep 11 05:39:26 AM UTC 24 31966517 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.2301794676 Sep 11 05:39:23 AM UTC 24 Sep 11 05:39:26 AM UTC 24 355547043 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.3517991133 Sep 11 05:39:35 AM UTC 24 Sep 11 05:39:37 AM UTC 24 57148559 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1801316653 Sep 11 05:39:22 AM UTC 24 Sep 11 05:39:26 AM UTC 24 793652480 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.1284830129 Sep 11 05:39:24 AM UTC 24 Sep 11 05:39:26 AM UTC 24 59197400 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.788086265 Sep 11 05:39:25 AM UTC 24 Sep 11 05:39:27 AM UTC 24 69844873 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.806322442 Sep 11 05:39:25 AM UTC 24 Sep 11 05:39:27 AM UTC 24 207125596 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.1295749100 Sep 11 05:39:24 AM UTC 24 Sep 11 05:39:27 AM UTC 24 38152754 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.4109820101 Sep 11 05:39:24 AM UTC 24 Sep 11 05:39:27 AM UTC 24 235042556 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.2963973221 Sep 11 05:39:25 AM UTC 24 Sep 11 05:39:27 AM UTC 24 47590101 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.1207014504 Sep 11 05:39:33 AM UTC 24 Sep 11 05:39:35 AM UTC 24 243704393 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.1116579129 Sep 11 05:39:24 AM UTC 24 Sep 11 05:39:28 AM UTC 24 862068651 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.4067139994 Sep 11 05:39:26 AM UTC 24 Sep 11 05:39:28 AM UTC 24 38335525 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.3427062340 Sep 11 05:39:26 AM UTC 24 Sep 11 05:39:28 AM UTC 24 28341059 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.176523897 Sep 11 05:39:26 AM UTC 24 Sep 11 05:39:28 AM UTC 24 32250762 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.1565660438 Sep 11 05:39:26 AM UTC 24 Sep 11 05:39:28 AM UTC 24 128779314 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.2177191351 Sep 11 05:39:26 AM UTC 24 Sep 11 05:39:28 AM UTC 24 50360759 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.656558590 Sep 11 05:39:26 AM UTC 24 Sep 11 05:39:28 AM UTC 24 82521919 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.362044697 Sep 11 05:39:26 AM UTC 24 Sep 11 05:39:29 AM UTC 24 203320887 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2482735395 Sep 11 05:39:25 AM UTC 24 Sep 11 05:39:29 AM UTC 24 840503737 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.3512121514 Sep 11 05:39:28 AM UTC 24 Sep 11 05:39:30 AM UTC 24 72896701 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.2656184617 Sep 11 05:39:28 AM UTC 24 Sep 11 05:39:30 AM UTC 24 118325273 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.1302465673 Sep 11 05:39:28 AM UTC 24 Sep 11 05:39:30 AM UTC 24 35231013 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.3878501401 Sep 11 05:39:28 AM UTC 24 Sep 11 05:39:30 AM UTC 24 60289410 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.2895242816 Sep 11 05:39:28 AM UTC 24 Sep 11 05:39:30 AM UTC 24 54430797 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.1056759559 Sep 11 05:39:28 AM UTC 24 Sep 11 05:39:31 AM UTC 24 81134149 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.3260325173 Sep 11 05:39:28 AM UTC 24 Sep 11 05:39:31 AM UTC 24 330582745 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.444094708 Sep 11 05:39:24 AM UTC 24 Sep 11 05:39:31 AM UTC 24 947591997 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.468077414 Sep 11 05:39:28 AM UTC 24 Sep 11 05:39:31 AM UTC 24 179018904 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.1654780225 Sep 11 05:39:28 AM UTC 24 Sep 11 05:39:31 AM UTC 24 313639513 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1227171316 Sep 11 05:39:26 AM UTC 24 Sep 11 05:39:31 AM UTC 24 777254711 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.2672295290 Sep 11 05:39:30 AM UTC 24 Sep 11 05:39:32 AM UTC 24 31618131 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.270492123 Sep 11 05:39:30 AM UTC 24 Sep 11 05:39:32 AM UTC 24 38650413 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.3747345575 Sep 11 05:39:30 AM UTC 24 Sep 11 05:39:32 AM UTC 24 111985267 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1549061522 Sep 11 05:39:29 AM UTC 24 Sep 11 05:39:32 AM UTC 24 76305266 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.3340742419 Sep 11 05:39:30 AM UTC 24 Sep 11 05:39:32 AM UTC 24 112309847 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.250545700 Sep 11 05:39:28 AM UTC 24 Sep 11 05:39:32 AM UTC 24 930985338 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.545846910 Sep 11 05:39:30 AM UTC 24 Sep 11 05:39:32 AM UTC 24 210634392 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1769027629 Sep 11 05:39:29 AM UTC 24 Sep 11 05:39:33 AM UTC 24 2556591120 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.2175862375 Sep 11 05:39:31 AM UTC 24 Sep 11 05:39:33 AM UTC 24 68945777 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.4097566523 Sep 11 05:39:31 AM UTC 24 Sep 11 05:39:34 AM UTC 24 66049326 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.3194862930 Sep 11 05:39:32 AM UTC 24 Sep 11 05:39:34 AM UTC 24 75805602 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.1230914790 Sep 11 05:39:31 AM UTC 24 Sep 11 05:39:34 AM UTC 24 111296684 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.4034925950 Sep 11 05:39:32 AM UTC 24 Sep 11 05:39:34 AM UTC 24 46974809 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.2279869952 Sep 11 05:39:32 AM UTC 24 Sep 11 05:39:34 AM UTC 24 122024481 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.3615579049 Sep 11 05:39:31 AM UTC 24 Sep 11 05:39:34 AM UTC 24 475609814 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2093008767 Sep 11 05:39:29 AM UTC 24 Sep 11 05:39:34 AM UTC 24 887958121 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.1562225105 Sep 11 05:39:32 AM UTC 24 Sep 11 05:39:35 AM UTC 24 259188965 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.3084499732 Sep 11 05:39:35 AM UTC 24 Sep 11 05:39:38 AM UTC 24 198233164 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.1979895972 Sep 11 05:39:33 AM UTC 24 Sep 11 05:39:35 AM UTC 24 32236453 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.815497885 Sep 11 05:39:28 AM UTC 24 Sep 11 05:39:35 AM UTC 24 5494767233 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.416463474 Sep 11 05:39:31 AM UTC 24 Sep 11 05:39:35 AM UTC 24 1283560868 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.1689774080 Sep 11 05:39:34 AM UTC 24 Sep 11 05:39:35 AM UTC 24 62624376 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.4195476305 Sep 11 05:39:33 AM UTC 24 Sep 11 05:39:36 AM UTC 24 40016590 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.73459927 Sep 11 05:39:33 AM UTC 24 Sep 11 05:39:36 AM UTC 24 178781528 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.825086561 Sep 11 05:39:34 AM UTC 24 Sep 11 05:39:36 AM UTC 24 51376147 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.239420078 Sep 11 05:39:34 AM UTC 24 Sep 11 05:39:36 AM UTC 24 407368515 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.3913664043 Sep 11 05:39:33 AM UTC 24 Sep 11 05:39:36 AM UTC 24 206032917 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3217718477 Sep 11 05:39:33 AM UTC 24 Sep 11 05:39:37 AM UTC 24 2711272510 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.1234565063 Sep 11 05:39:35 AM UTC 24 Sep 11 05:39:37 AM UTC 24 71818201 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.2059645568 Sep 11 05:39:35 AM UTC 24 Sep 11 05:39:38 AM UTC 24 111152895 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.3215641899 Sep 11 05:39:35 AM UTC 24 Sep 11 05:39:38 AM UTC 24 275283770 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1923848146 Sep 11 05:39:33 AM UTC 24 Sep 11 05:39:38 AM UTC 24 850523644 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.113205814 Sep 11 05:39:35 AM UTC 24 Sep 11 05:39:38 AM UTC 24 560420248 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.4119640721 Sep 11 05:39:35 AM UTC 24 Sep 11 05:39:39 AM UTC 24 656440218 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.3379823987 Sep 11 05:39:51 AM UTC 24 Sep 11 05:39:53 AM UTC 24 76385894 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.604869272 Sep 11 05:39:38 AM UTC 24 Sep 11 05:39:40 AM UTC 24 79279358 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.4149238065 Sep 11 05:39:38 AM UTC 24 Sep 11 05:39:40 AM UTC 24 45454236 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1290166273 Sep 11 05:39:38 AM UTC 24 Sep 11 05:39:40 AM UTC 24 47180656 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.3741260751 Sep 11 05:39:38 AM UTC 24 Sep 11 05:39:40 AM UTC 24 183415631 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.1354223996 Sep 11 05:39:38 AM UTC 24 Sep 11 05:39:40 AM UTC 24 83941699 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.272430097 Sep 11 05:39:38 AM UTC 24 Sep 11 05:39:40 AM UTC 24 51425189 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.451556147 Sep 11 05:39:38 AM UTC 24 Sep 11 05:39:40 AM UTC 24 69772015 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.3152201498 Sep 11 05:39:38 AM UTC 24 Sep 11 05:39:40 AM UTC 24 53259165 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.2640957323 Sep 11 05:39:38 AM UTC 24 Sep 11 05:39:40 AM UTC 24 110507690 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.3713180731 Sep 11 05:39:38 AM UTC 24 Sep 11 05:39:40 AM UTC 24 67661739 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.1647940907 Sep 11 05:39:38 AM UTC 24 Sep 11 05:39:40 AM UTC 24 114768026 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.3742475504 Sep 11 05:39:38 AM UTC 24 Sep 11 05:39:41 AM UTC 24 210386677 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1421557069 Sep 11 05:39:38 AM UTC 24 Sep 11 05:39:41 AM UTC 24 1309949665 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.2633365423 Sep 11 05:39:40 AM UTC 24 Sep 11 05:39:42 AM UTC 24 30208662 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.46125503 Sep 11 05:39:38 AM UTC 24 Sep 11 05:39:42 AM UTC 24 863364466 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.1933786127 Sep 11 05:39:51 AM UTC 24 Sep 11 05:39:53 AM UTC 24 56262216 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.2520566038 Sep 11 05:39:40 AM UTC 24 Sep 11 05:39:42 AM UTC 24 76924724 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.611927570 Sep 11 05:39:38 AM UTC 24 Sep 11 05:39:42 AM UTC 24 686316753 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.2375367831 Sep 11 05:39:40 AM UTC 24 Sep 11 05:39:42 AM UTC 24 216431160 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.1126110771 Sep 11 05:39:40 AM UTC 24 Sep 11 05:39:42 AM UTC 24 27196899 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.807143526 Sep 11 05:39:40 AM UTC 24 Sep 11 05:39:43 AM UTC 24 157693850 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.2020607514 Sep 11 05:39:41 AM UTC 24 Sep 11 05:39:43 AM UTC 24 87259329 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.1076598357 Sep 11 05:39:40 AM UTC 24 Sep 11 05:39:43 AM UTC 24 238757418 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.2365526995 Sep 11 05:39:40 AM UTC 24 Sep 11 05:39:44 AM UTC 24 340709540 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.3426012393 Sep 11 05:39:42 AM UTC 24 Sep 11 05:39:44 AM UTC 24 141652820 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.1447286775 Sep 11 05:39:42 AM UTC 24 Sep 11 05:39:44 AM UTC 24 62550955 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1365869097 Sep 11 05:39:42 AM UTC 24 Sep 11 05:39:44 AM UTC 24 28922650 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.970923037 Sep 11 05:39:43 AM UTC 24 Sep 11 05:39:45 AM UTC 24 44394213 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.2266356622 Sep 11 05:39:42 AM UTC 24 Sep 11 05:39:45 AM UTC 24 41615694 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.3479878881 Sep 11 05:39:43 AM UTC 24 Sep 11 05:39:45 AM UTC 24 89901501 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.1668917863 Sep 11 05:39:42 AM UTC 24 Sep 11 05:39:45 AM UTC 24 110677045 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2256932501 Sep 11 05:39:41 AM UTC 24 Sep 11 05:39:45 AM UTC 24 834575455 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.2954517803 Sep 11 05:39:43 AM UTC 24 Sep 11 05:39:45 AM UTC 24 57734528 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.659534462 Sep 11 05:39:41 AM UTC 24 Sep 11 05:39:45 AM UTC 24 928961486 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.3632900084 Sep 11 05:39:43 AM UTC 24 Sep 11 05:39:45 AM UTC 24 104455987 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.2265179533 Sep 11 05:39:43 AM UTC 24 Sep 11 05:39:45 AM UTC 24 330468273 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.3720544259 Sep 11 05:39:45 AM UTC 24 Sep 11 05:39:47 AM UTC 24 30947251 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.466091903 Sep 11 05:39:45 AM UTC 24 Sep 11 05:39:47 AM UTC 24 127360129 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1269975744 Sep 11 05:39:45 AM UTC 24 Sep 11 05:39:47 AM UTC 24 38672634 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.969013534 Sep 11 05:39:44 AM UTC 24 Sep 11 05:39:47 AM UTC 24 240146162 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.2300111402 Sep 11 05:39:45 AM UTC 24 Sep 11 05:39:47 AM UTC 24 172658177 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.2565808528 Sep 11 05:39:44 AM UTC 24 Sep 11 05:39:47 AM UTC 24 178947975 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.3353265390 Sep 11 05:39:45 AM UTC 24 Sep 11 05:39:47 AM UTC 24 135817759 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.752667994 Sep 11 05:39:45 AM UTC 24 Sep 11 05:39:48 AM UTC 24 1375126348 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.1037001280 Sep 11 05:39:46 AM UTC 24 Sep 11 05:39:48 AM UTC 24 115382523 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.1381855953 Sep 11 05:39:43 AM UTC 24 Sep 11 05:39:48 AM UTC 24 2899650362 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.73028206 Sep 11 05:39:47 AM UTC 24 Sep 11 05:39:48 AM UTC 24 75500726 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.2917321938 Sep 11 05:39:47 AM UTC 24 Sep 11 05:39:49 AM UTC 24 113957000 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.2567099974 Sep 11 05:39:46 AM UTC 24 Sep 11 05:39:49 AM UTC 24 108519509 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.1595791829 Sep 11 05:39:47 AM UTC 24 Sep 11 05:39:49 AM UTC 24 167472597 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.221399039 Sep 11 05:39:47 AM UTC 24 Sep 11 05:39:49 AM UTC 24 123997727 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.3183095152 Sep 11 05:39:47 AM UTC 24 Sep 11 05:39:49 AM UTC 24 43599876 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.2761315427 Sep 11 05:39:47 AM UTC 24 Sep 11 05:39:49 AM UTC 24 38933398 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1181194353 Sep 11 05:39:47 AM UTC 24 Sep 11 05:39:49 AM UTC 24 134556292 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.3928954424 Sep 11 05:39:47 AM UTC 24 Sep 11 05:39:49 AM UTC 24 209223752 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.273099939 Sep 11 05:39:45 AM UTC 24 Sep 11 05:39:50 AM UTC 24 976654242 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.2175755837 Sep 11 05:39:35 AM UTC 24 Sep 11 05:39:50 AM UTC 24 5398717115 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.3308617896 Sep 11 05:39:49 AM UTC 24 Sep 11 05:39:51 AM UTC 24 30124876 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.3334859682 Sep 11 05:39:49 AM UTC 24 Sep 11 05:39:51 AM UTC 24 23771418 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.999732273 Sep 11 05:39:49 AM UTC 24 Sep 11 05:39:51 AM UTC 24 416821339 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.2015170061 Sep 11 05:39:49 AM UTC 24 Sep 11 05:39:51 AM UTC 24 55856476 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.1721573466 Sep 11 05:39:49 AM UTC 24 Sep 11 05:39:51 AM UTC 24 107480307 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.991091213 Sep 11 05:39:43 AM UTC 24 Sep 11 05:39:51 AM UTC 24 1826823810 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.127267421 Sep 11 05:39:47 AM UTC 24 Sep 11 05:39:52 AM UTC 24 2004747956 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.2123411998 Sep 11 05:39:40 AM UTC 24 Sep 11 05:39:52 AM UTC 24 4553635794 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1325245852 Sep 11 05:39:49 AM UTC 24 Sep 11 05:39:52 AM UTC 24 1022233575 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.2104718595 Sep 11 05:39:51 AM UTC 24 Sep 11 05:39:53 AM UTC 24 53331785 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3814957365 Sep 11 05:39:49 AM UTC 24 Sep 11 05:39:53 AM UTC 24 987664243 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.2860876321 Sep 11 05:39:51 AM UTC 24 Sep 11 05:39:53 AM UTC 24 57883250 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.3724865834 Sep 11 05:39:51 AM UTC 24 Sep 11 05:39:53 AM UTC 24 100890197 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.3995511631 Sep 11 05:39:51 AM UTC 24 Sep 11 05:39:53 AM UTC 24 61383393 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.1523865694 Sep 11 05:39:51 AM UTC 24 Sep 11 05:39:53 AM UTC 24 104133033 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.3075858196 Sep 11 05:39:51 AM UTC 24 Sep 11 05:39:53 AM UTC 24 122947137 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.3869093878 Sep 11 05:39:51 AM UTC 24 Sep 11 05:39:53 AM UTC 24 38747439 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.1433927978 Sep 11 05:39:51 AM UTC 24 Sep 11 05:39:53 AM UTC 24 52822394 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.1243811001 Sep 11 05:39:51 AM UTC 24 Sep 11 05:39:54 AM UTC 24 290433930 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.4137162636 Sep 11 05:39:51 AM UTC 24 Sep 11 05:39:54 AM UTC 24 372650300 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.218608612 Sep 11 05:39:51 AM UTC 24 Sep 11 05:39:54 AM UTC 24 428273011 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.463360069 Sep 11 05:39:47 AM UTC 24 Sep 11 05:39:57 AM UTC 24 2427007995 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.168444150 Sep 11 05:39:55 AM UTC 24 Sep 11 05:39:57 AM UTC 24 90091293 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.1216805123 Sep 11 05:39:55 AM UTC 24 Sep 11 05:39:57 AM UTC 24 76605245 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.74659079 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:11 AM UTC 24 41918157 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.267256268 Sep 11 05:39:55 AM UTC 24 Sep 11 05:39:57 AM UTC 24 28669938 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.1041137656 Sep 11 05:39:55 AM UTC 24 Sep 11 05:39:57 AM UTC 24 74180836 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.3668718928 Sep 11 05:39:55 AM UTC 24 Sep 11 05:39:57 AM UTC 24 71150107 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.1308683142 Sep 11 05:39:55 AM UTC 24 Sep 11 05:39:57 AM UTC 24 51059386 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.187737891 Sep 11 05:39:55 AM UTC 24 Sep 11 05:39:57 AM UTC 24 120879223 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.167978854 Sep 11 05:39:55 AM UTC 24 Sep 11 05:39:57 AM UTC 24 40155634 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.2577632825 Sep 11 05:39:55 AM UTC 24 Sep 11 05:39:58 AM UTC 24 128762514 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.3848816032 Sep 11 05:39:56 AM UTC 24 Sep 11 05:39:58 AM UTC 24 69388449 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3215514182 Sep 11 05:39:56 AM UTC 24 Sep 11 05:39:58 AM UTC 24 31960435 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.2794807317 Sep 11 05:39:55 AM UTC 24 Sep 11 05:39:58 AM UTC 24 403684813 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.306633462 Sep 11 05:39:55 AM UTC 24 Sep 11 05:39:58 AM UTC 24 229698127 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.3178802509 Sep 11 05:39:55 AM UTC 24 Sep 11 05:39:58 AM UTC 24 97509409 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1418262806 Sep 11 05:39:56 AM UTC 24 Sep 11 05:39:58 AM UTC 24 250722073 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.4222853634 Sep 11 05:39:56 AM UTC 24 Sep 11 05:39:58 AM UTC 24 391076475 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.3927118551 Sep 11 05:39:55 AM UTC 24 Sep 11 05:39:58 AM UTC 24 248784349 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1572799177 Sep 11 05:39:55 AM UTC 24 Sep 11 05:39:58 AM UTC 24 969333371 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.159424567 Sep 11 05:39:55 AM UTC 24 Sep 11 05:39:59 AM UTC 24 895978668 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.814905760 Sep 11 05:39:56 AM UTC 24 Sep 11 05:40:00 AM UTC 24 1132888661 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3035301422 Sep 11 05:39:56 AM UTC 24 Sep 11 05:40:00 AM UTC 24 890489436 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.401579473 Sep 11 05:39:55 AM UTC 24 Sep 11 05:40:00 AM UTC 24 569684596 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.3612324474 Sep 11 05:40:00 AM UTC 24 Sep 11 05:40:02 AM UTC 24 140617962 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.2108172457 Sep 11 05:40:00 AM UTC 24 Sep 11 05:40:02 AM UTC 24 270073623 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.1348581635 Sep 11 05:40:00 AM UTC 24 Sep 11 05:40:02 AM UTC 24 45236002 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.2882660568 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:11 AM UTC 24 122146981 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.805664372 Sep 11 05:40:00 AM UTC 24 Sep 11 05:40:02 AM UTC 24 210649257 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.46908958 Sep 11 05:40:00 AM UTC 24 Sep 11 05:40:02 AM UTC 24 115327403 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.911140077 Sep 11 05:40:00 AM UTC 24 Sep 11 05:40:02 AM UTC 24 62354850 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3518647511 Sep 11 05:40:00 AM UTC 24 Sep 11 05:40:03 AM UTC 24 303487924 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.2514040208 Sep 11 05:40:01 AM UTC 24 Sep 11 05:40:03 AM UTC 24 30712682 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.2927188102 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:11 AM UTC 24 48059006 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.3519500388 Sep 11 05:40:01 AM UTC 24 Sep 11 05:40:03 AM UTC 24 110643300 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.804192714 Sep 11 05:40:01 AM UTC 24 Sep 11 05:40:03 AM UTC 24 149695669 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.698190577 Sep 11 05:40:01 AM UTC 24 Sep 11 05:40:03 AM UTC 24 111298742 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.2485289679 Sep 11 05:40:01 AM UTC 24 Sep 11 05:40:03 AM UTC 24 41918597 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1105409850 Sep 11 05:40:01 AM UTC 24 Sep 11 05:40:03 AM UTC 24 178521082 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.1191779743 Sep 11 05:40:01 AM UTC 24 Sep 11 05:40:03 AM UTC 24 232058529 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.4289884802 Sep 11 05:40:01 AM UTC 24 Sep 11 05:40:04 AM UTC 24 153346345 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.3858813979 Sep 11 05:40:01 AM UTC 24 Sep 11 05:40:04 AM UTC 24 361855623 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.3167218691 Sep 11 05:39:51 AM UTC 24 Sep 11 05:40:05 AM UTC 24 2701182189 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.3470211701 Sep 11 05:39:55 AM UTC 24 Sep 11 05:40:05 AM UTC 24 7051355588 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2433417371 Sep 11 05:40:01 AM UTC 24 Sep 11 05:40:05 AM UTC 24 936618109 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.2348908121 Sep 11 05:40:01 AM UTC 24 Sep 11 05:40:05 AM UTC 24 2551463733 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.3866274545 Sep 11 05:40:04 AM UTC 24 Sep 11 05:40:05 AM UTC 24 76466244 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.1826822289 Sep 11 05:40:04 AM UTC 24 Sep 11 05:40:05 AM UTC 24 33594124 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1981357991 Sep 11 05:40:01 AM UTC 24 Sep 11 05:40:06 AM UTC 24 848604685 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.1158642674 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:12 AM UTC 24 322664377 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.3910328846 Sep 11 05:40:04 AM UTC 24 Sep 11 05:40:06 AM UTC 24 64483885 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.3283448825 Sep 11 05:40:04 AM UTC 24 Sep 11 05:40:06 AM UTC 24 381638362 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.3554226235 Sep 11 05:40:04 AM UTC 24 Sep 11 05:40:06 AM UTC 24 77169957 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.185021997 Sep 11 05:40:04 AM UTC 24 Sep 11 05:40:06 AM UTC 24 115276984 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.2727007849 Sep 11 05:40:04 AM UTC 24 Sep 11 05:40:06 AM UTC 24 114120031 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.1032039529 Sep 11 05:40:04 AM UTC 24 Sep 11 05:40:06 AM UTC 24 105394530 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.1949913439 Sep 11 05:40:04 AM UTC 24 Sep 11 05:40:06 AM UTC 24 81651816 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.2833503437 Sep 11 05:40:04 AM UTC 24 Sep 11 05:40:06 AM UTC 24 160356395 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.65705395 Sep 11 05:40:04 AM UTC 24 Sep 11 05:40:06 AM UTC 24 91482109 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.238524767 Sep 11 05:40:04 AM UTC 24 Sep 11 05:40:06 AM UTC 24 578543700 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.2744145114 Sep 11 05:40:04 AM UTC 24 Sep 11 05:40:07 AM UTC 24 217524470 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3206746159 Sep 11 05:40:04 AM UTC 24 Sep 11 05:40:07 AM UTC 24 1201174679 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.1836411353 Sep 11 05:40:00 AM UTC 24 Sep 11 05:40:08 AM UTC 24 2063204216 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.2506351852 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:11 AM UTC 24 58240517 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.3535713549 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:11 AM UTC 24 55614994 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.2154116134 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:11 AM UTC 24 44105852 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.3336011819 Sep 11 05:40:08 AM UTC 24 Sep 11 05:40:11 AM UTC 24 52865041 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.93568807 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:11 AM UTC 24 742647107 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.3748910373 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:11 AM UTC 24 396870930 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.3590749620 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:12 AM UTC 24 57191278 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.1727869774 Sep 11 05:40:31 AM UTC 24 Sep 11 05:40:34 AM UTC 24 33944938 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.2440615855 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:12 AM UTC 24 71461306 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.3133379955 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:12 AM UTC 24 29571355 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.2325047081 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:12 AM UTC 24 103522754 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.2963280489 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:12 AM UTC 24 65026681 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.2583309794 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:12 AM UTC 24 107122887 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.2718910489 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:12 AM UTC 24 52114499 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.580749780 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:12 AM UTC 24 401283259 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.3743925989 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:12 AM UTC 24 194251600 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.2029646428 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:13 AM UTC 24 250069326 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.1269419497 Sep 11 05:40:11 AM UTC 24 Sep 11 05:40:13 AM UTC 24 71642674 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1501159608 Sep 11 05:40:08 AM UTC 24 Sep 11 05:40:13 AM UTC 24 1097605361 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2046993402 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:14 AM UTC 24 899340741 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1557741933 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:14 AM UTC 24 901660417 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.2596560257 Sep 11 05:40:15 AM UTC 24 Sep 11 05:40:16 AM UTC 24 43939888 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.1016418023 Sep 11 05:40:14 AM UTC 24 Sep 11 05:40:16 AM UTC 24 141179359 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_smoke.473359787 Sep 11 05:40:37 AM UTC 24 Sep 11 05:40:39 AM UTC 24 38994349 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.1040109260 Sep 11 05:40:15 AM UTC 24 Sep 11 05:40:17 AM UTC 24 31987140 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all_with_rand_reset.2594244647 Sep 11 05:40:09 AM UTC 24 Sep 11 05:40:17 AM UTC 24 4574321939 ps
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