Group : pwrmgr_env_pkg::pwrmgr_env_cov::reset_wakeup_distance_cg
Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::reset_wakeup_distance_cg
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
9 |
0 |
9 |
100.00 |
Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::reset_wakeup_distance_cg
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cycles_cp |
9 |
0 |
9 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cycles_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
9 |
0 |
9 |
100.00 |
User Defined Bins for cycles_cp
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| far |
0 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| close[-4] |
392 |
1 |
|
|
T7 |
2 |
|
T16 |
3 |
|
T32 |
3 |
| close[-3] |
726 |
1 |
|
|
T7 |
1 |
|
T16 |
4 |
|
T32 |
6 |
| close[-2] |
1168 |
1 |
|
|
T7 |
1 |
|
T16 |
6 |
|
T32 |
4 |
| close[-1] |
1466 |
1 |
|
|
T7 |
1 |
|
T16 |
5 |
|
T32 |
7 |
| close[0] |
1814 |
1 |
|
|
T7 |
6 |
|
T16 |
11 |
|
T32 |
10 |
| close[1] |
1492 |
1 |
|
|
T7 |
4 |
|
T16 |
8 |
|
T32 |
7 |
| close[2] |
1087 |
1 |
|
|
T7 |
2 |
|
T16 |
9 |
|
T32 |
8 |
| close[3] |
695 |
1 |
|
|
T7 |
2 |
|
T16 |
2 |
|
T32 |
4 |
| close[4] |
352 |
1 |
|
|
T7 |
1 |
|
T16 |
2 |
|
T32 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |