Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23833

1

T1

2

T3

8

T5

7

auto[1]

23149

1

T2

2

T3

8

T5

6

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23989

1

T1

2

T3

6

T5

6

auto[1]

22993

1

T2

2

T3

10

T5

7

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22985

1

T2

2

T3

4

T5

6

auto[1]

23997

1

T1

2

T3

12

T5

7

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26273

1

T1

1

T2

1

T3

8

auto[1]

20709

1

T1

1

T2

1

T3

8

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22990

1

T2

2

T3

10

T5

8

auto[1]

23992

1

T1

2

T3

6

T5

5

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24250

1

T1

2

T2

2

T3

10

auto[1]

22732

1

T3

6

T5

8

T6

10

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

805

1

T14

1

T15

1

T16

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

628

1

T14

1

T15

1

T36

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

802

1

T10

1

T14

3

T15

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

630

1

T10

1

T14

3

T15

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

822

1

T6

3

T14

1

T32

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

656

1

T6

3

T14

1

T32

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1282

1

T1

1

T6

2

T14

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1093

1

T1

1

T6

2

T14

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

772

1

T14

1

T16

2

T32

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

599

1

T14

1

T16

2

T32

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

793

1

T3

1

T5

1

T14

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

635

1

T3

1

T14

2

T15

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

827

1

T5

1

T6

1

T14

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

657

1

T6

1

T14

1

T15

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

809

1

T10

1

T15

2

T16

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

652

1

T10

1

T15

2

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

784

1

T3

1

T10

1

T14

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

613

1

T3

1

T10

1

T14

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

807

1

T3

1

T5

3

T6

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

621

1

T3

1

T6

1

T14

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

799

1

T14

2

T32

1

T36

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

626

1

T14

2

T32

1

T36

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

847

1

T3

1

T14

1

T15

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

647

1

T3

1

T14

1

T15

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

791

1

T14

1

T15

2

T17

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

632

1

T14

1

T15

2

T27

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

801

1

T6

1

T14

1

T15

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

615

1

T6

1

T14

1

T15

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

821

1

T5

1

T10

2

T14

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

643

1

T10

1

T14

2

T15

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

755

1

T5

1

T10

2

T14

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

569

1

T14

2

T33

1

T36

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

842

1

T5

1

T10

1

T14

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

687

1

T14

3

T15

8

T16

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

820

1

T10

1

T14

1

T15

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

661

1

T10

1

T14

1

T15

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

799

1

T14

1

T15

2

T16

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

633

1

T14

1

T15

2

T16

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

771

1

T3

1

T6

1

T10

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

607

1

T3

1

T6

1

T15

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

771

1

T3

1

T5

2

T6

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

615

1

T3

1

T6

1

T14

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

800

1

T14

1

T15

4

T16

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

642

1

T14

1

T15

4

T32

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

769

1

T10

1

T15

2

T16

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

612

1

T10

1

T15

2

T16

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

837

1

T5

1

T6

1

T10

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

661

1

T6

1

T10

1

T15

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

850

1

T2

1

T10

1

T14

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

653

1

T2

1

T10

1

T14

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

866

1

T10

1

T14

3

T79

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

657

1

T10

1

T14

3

T79

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

825

1

T5

1

T10

1

T14

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

641

1

T10

1

T14

5

T15

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

822

1

T3

1

T6

3

T10

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

654

1

T3

1

T6

3

T15

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

781

1

T14

1

T15

1

T32

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

615

1

T14

1

T15

1

T32

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

801

1

T3

1

T5

1

T6

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

601

1

T3

1

T6

1

T14

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

785

1

T10

1

T14

5

T15

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

632

1

T14

5

T15

4

T79

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

817

1

T14

1

T15

1

T36

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

622

1

T14

1

T15

1

T36

3