Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.96 98.21 96.58 99.62 96.00 96.32 100.00 99.02


Total tests in report: 1118
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
76.36 76.36 95.69 95.69 78.74 78.74 61.11 61.11 60.00 60.00 92.84 92.84 90.79 90.79 55.32 55.32 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.2024430595
84.52 8.17 96.10 0.41 85.31 6.56 85.78 24.67 82.00 22.00 93.42 0.58 92.11 1.32 56.96 1.64 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.3428986362
89.61 5.09 96.83 0.73 88.30 3.00 87.01 1.22 86.00 4.00 93.81 0.39 94.47 2.37 80.85 23.90 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.858326207
91.76 2.15 96.99 0.16 89.44 1.14 96.61 9.60 88.00 2.00 94.58 0.77 95.53 1.05 81.18 0.33 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.2227626024
92.96 1.20 97.72 0.73 93.01 3.57 96.80 0.19 88.00 0.00 95.36 0.77 95.53 0.00 84.29 3.11 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3166231492
94.14 1.19 97.72 0.00 93.15 0.14 96.80 0.00 96.00 8.00 95.36 0.00 95.53 0.00 84.45 0.16 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.1484597750
95.31 1.16 97.72 0.00 93.15 0.00 99.62 2.82 96.00 0.00 95.55 0.19 96.05 0.53 89.03 4.58 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.946928231
96.17 0.86 97.80 0.08 93.72 0.57 99.62 0.00 96.00 0.00 95.74 0.19 96.84 0.79 93.45 4.42 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all_with_rand_reset.821056660
96.46 0.29 98.05 0.24 93.87 0.14 99.62 0.00 96.00 0.00 95.74 0.00 96.84 0.00 95.09 1.64 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.903247052
96.72 0.26 98.05 0.00 93.87 0.00 99.62 0.00 96.00 0.00 95.74 0.00 98.68 1.84 95.09 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.2115690791
96.99 0.26 98.21 0.16 94.44 0.57 99.62 0.00 96.00 0.00 96.32 0.58 99.21 0.53 95.09 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.1550076277
97.17 0.18 98.21 0.00 94.58 0.14 99.62 0.00 96.00 0.00 96.32 0.00 99.21 0.00 96.24 1.15 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.3531309124
97.35 0.18 98.21 0.00 95.86 1.28 99.62 0.00 96.00 0.00 96.32 0.00 99.21 0.00 96.24 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.449061970
97.49 0.14 98.21 0.00 96.01 0.14 99.62 0.00 96.00 0.00 96.32 0.00 99.21 0.00 97.05 0.82 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.4252688942
97.61 0.12 98.21 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.32 0.00 99.21 0.00 97.87 0.82 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.2371249420
97.68 0.08 98.21 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.32 0.00 99.74 0.53 97.87 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.1528165561
97.75 0.07 98.21 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.32 0.00 99.74 0.00 98.36 0.49 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.1252322444
97.80 0.05 98.21 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.32 0.00 99.74 0.00 98.69 0.33 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.2105770673
97.82 0.02 98.21 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.32 0.00 99.74 0.00 98.85 0.16 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1347932006
97.85 0.02 98.21 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.32 0.00 99.74 0.00 99.02 0.16 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_disable_rom_integrity_check.89951777
97.87 0.02 98.21 0.00 96.15 0.14 99.62 0.00 96.00 0.00 96.32 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.530401823
97.89 0.02 98.21 0.00 96.29 0.14 99.62 0.00 96.00 0.00 96.32 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.1672432838
97.91 0.02 98.21 0.00 96.43 0.14 99.62 0.00 96.00 0.00 96.32 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.737730492
97.93 0.02 98.21 0.00 96.58 0.14 99.62 0.00 96.00 0.00 96.32 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.2134503721

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2547186184
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.2075753830
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2659402791
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.23947337
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.3635858731
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.2204734587
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.63018673
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1462482004
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1710210687
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.415232120
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.589571963
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3656974910
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3546768599
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1008718522
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.3690759221
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1572842710
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.1080084472
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.3351409945
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2196881876
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.1203775382
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.715115692
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.2244113511
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.695689939
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3031419685
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.3711866372
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.2814422526
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.349878380
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.2229614521
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3781547552
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1055896210
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.3589040800
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.1110529388
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2642529270
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.3862456823
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.2263061541
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.733723229
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.2202964841
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.435346951
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.4141525785
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.89283090
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1881776803
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3999499578
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3777911144
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.2909298636
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.2208233128
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.3345933438
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.805359874
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.3749435887
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.1218842697
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.137844186
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1847558778
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.2987946583
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2550977684
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.341817818
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.3421528202
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.2727639349
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.992687344
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.1800045278
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.1586967150
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.4226848650
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.2645005319
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.2082804159
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.844330179
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.1820552879
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.1061628509
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3543897095
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.50469920
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.2308261775
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1188821304
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.2689556602
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.405846333
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2716599700
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3943133207
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.617325726
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.974739727
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.2762978694
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.2501594639
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.254842583
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.454858315
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.922515332
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.2714901852
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.3542265081
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.1601640423
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.3305241686
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.4038129102
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.1463135697
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.2813105988
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.2181216092
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.1306989246
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3042644062
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1602761738
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.4056066132
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.2860327344
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/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.343672473
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.3657117707
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/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.3698339078
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.2839874131
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.3932402966
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.1767524781
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.2591298440
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.2706154758
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.952207105
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1862791309
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.3096698496
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.262648941
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.491385854
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3904451764
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/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.846565967
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.3499531835
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.3683087308
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.4153740716
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.3636647042
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.2702223436
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.3205002132
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.287748771
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.3755318753
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.3808822054
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.3912441505
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.508396298
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3705915023
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2981802527
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/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.1401526745
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.2055562089
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.4138970511
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.3315931418
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.1569599775
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.2599743025
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.2453470512
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.717691625
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2705623616
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.3400437682
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.523409485
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3125186026
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1095995956
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2340308371
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.4051370806
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.2149418815
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.3244889782
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.88303022
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.2916003433



Total test records in report: 1118
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.1243264909 Sep 18 07:46:21 PM UTC 24 Sep 18 07:46:23 PM UTC 24 39942907 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.1365387026 Sep 18 07:46:22 PM UTC 24 Sep 18 07:46:24 PM UTC 24 69703563 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.1333974410 Sep 18 07:46:22 PM UTC 24 Sep 18 07:46:25 PM UTC 24 122929598 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.3004727731 Sep 18 07:46:22 PM UTC 24 Sep 18 07:46:25 PM UTC 24 93812523 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.1548999524 Sep 18 07:46:23 PM UTC 24 Sep 18 07:46:26 PM UTC 24 115195523 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.2024430595 Sep 18 07:46:23 PM UTC 24 Sep 18 07:46:26 PM UTC 24 300751508 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.1550076277 Sep 18 07:46:25 PM UTC 24 Sep 18 07:46:27 PM UTC 24 57152530 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.69635714 Sep 18 07:46:25 PM UTC 24 Sep 18 07:46:27 PM UTC 24 70168410 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.1162580557 Sep 18 07:46:26 PM UTC 24 Sep 18 07:46:28 PM UTC 24 42275624 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.3531309124 Sep 18 07:46:26 PM UTC 24 Sep 18 07:46:28 PM UTC 24 147827252 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3789332822 Sep 18 07:46:25 PM UTC 24 Sep 18 07:46:29 PM UTC 24 814910797 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.737730492 Sep 18 07:46:27 PM UTC 24 Sep 18 07:46:29 PM UTC 24 91395570 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3161266014 Sep 18 07:46:25 PM UTC 24 Sep 18 07:46:29 PM UTC 24 1046216465 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.3266999189 Sep 18 07:46:27 PM UTC 24 Sep 18 07:46:29 PM UTC 24 113120570 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.2490631593 Sep 18 07:46:28 PM UTC 24 Sep 18 07:46:30 PM UTC 24 61409407 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.3428986362 Sep 18 07:46:28 PM UTC 24 Sep 18 07:46:31 PM UTC 24 115826079 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.855472253 Sep 18 07:46:57 PM UTC 24 Sep 18 07:47:00 PM UTC 24 70713114 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.1484597750 Sep 18 07:46:30 PM UTC 24 Sep 18 07:46:33 PM UTC 24 75134543 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.2654089745 Sep 18 07:46:31 PM UTC 24 Sep 18 07:46:33 PM UTC 24 170479671 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.766527492 Sep 18 07:46:31 PM UTC 24 Sep 18 07:46:33 PM UTC 24 53868832 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.3158708826 Sep 18 07:46:31 PM UTC 24 Sep 18 07:46:33 PM UTC 24 138825872 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.1528165561 Sep 18 07:46:31 PM UTC 24 Sep 18 07:46:34 PM UTC 24 556041798 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.2227626024 Sep 18 07:46:31 PM UTC 24 Sep 18 07:46:34 PM UTC 24 338016651 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.3740906525 Sep 18 07:46:32 PM UTC 24 Sep 18 07:46:34 PM UTC 24 249264923 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.757267061 Sep 18 07:46:32 PM UTC 24 Sep 18 07:46:35 PM UTC 24 181974183 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.1443858231 Sep 18 07:46:34 PM UTC 24 Sep 18 07:46:36 PM UTC 24 39783812 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.2424864598 Sep 18 07:46:34 PM UTC 24 Sep 18 07:46:36 PM UTC 24 39787438 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2842346820 Sep 18 07:46:34 PM UTC 24 Sep 18 07:46:36 PM UTC 24 166799255 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.1754699476 Sep 18 07:46:36 PM UTC 24 Sep 18 07:46:37 PM UTC 24 105042339 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.850774361 Sep 18 07:46:36 PM UTC 24 Sep 18 07:46:38 PM UTC 24 32742758 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2601232389 Sep 18 07:46:34 PM UTC 24 Sep 18 07:46:38 PM UTC 24 981649645 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.2874892010 Sep 18 07:46:36 PM UTC 24 Sep 18 07:46:38 PM UTC 24 370197162 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.4121040823 Sep 18 07:46:36 PM UTC 24 Sep 18 07:46:38 PM UTC 24 300820565 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.946928231 Sep 18 07:46:34 PM UTC 24 Sep 18 07:46:38 PM UTC 24 1021040676 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.2492033598 Sep 18 07:46:37 PM UTC 24 Sep 18 07:46:39 PM UTC 24 72616613 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.1979749939 Sep 18 07:46:37 PM UTC 24 Sep 18 07:46:39 PM UTC 24 180711919 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.3796194125 Sep 18 07:46:37 PM UTC 24 Sep 18 07:46:39 PM UTC 24 119511063 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.858326207 Sep 18 07:46:31 PM UTC 24 Sep 18 07:46:39 PM UTC 24 4448346311 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.2856024221 Sep 18 07:46:43 PM UTC 24 Sep 18 07:46:45 PM UTC 24 55107158 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.2480742068 Sep 18 07:46:43 PM UTC 24 Sep 18 07:46:45 PM UTC 24 32550316 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.836552165 Sep 18 07:46:43 PM UTC 24 Sep 18 07:46:46 PM UTC 24 396735571 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.3118568377 Sep 18 07:46:43 PM UTC 24 Sep 18 07:46:46 PM UTC 24 61759164 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.192584738 Sep 18 07:46:43 PM UTC 24 Sep 18 07:46:46 PM UTC 24 171952467 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.2984349060 Sep 18 07:46:43 PM UTC 24 Sep 18 07:46:46 PM UTC 24 177028956 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.3092042876 Sep 18 07:46:43 PM UTC 24 Sep 18 07:46:46 PM UTC 24 84666584 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.937640628 Sep 18 07:46:43 PM UTC 24 Sep 18 07:46:46 PM UTC 24 449782057 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.2850779305 Sep 18 07:46:43 PM UTC 24 Sep 18 07:46:46 PM UTC 24 117753651 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3447283362 Sep 18 07:46:43 PM UTC 24 Sep 18 07:46:48 PM UTC 24 1117228631 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.3436116628 Sep 18 07:46:57 PM UTC 24 Sep 18 07:46:59 PM UTC 24 33226715 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.2427404518 Sep 18 07:46:47 PM UTC 24 Sep 18 07:46:49 PM UTC 24 33485518 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.770263062 Sep 18 07:46:47 PM UTC 24 Sep 18 07:46:49 PM UTC 24 125883923 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.1539083938 Sep 18 07:46:47 PM UTC 24 Sep 18 07:46:49 PM UTC 24 52353196 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.430073780 Sep 18 07:46:47 PM UTC 24 Sep 18 07:46:49 PM UTC 24 678128989 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.938854481 Sep 18 07:46:47 PM UTC 24 Sep 18 07:46:50 PM UTC 24 212861953 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.403977673 Sep 18 07:46:47 PM UTC 24 Sep 18 07:46:50 PM UTC 24 41974896 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.499145489 Sep 18 07:46:47 PM UTC 24 Sep 18 07:46:50 PM UTC 24 119239136 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.2622867457 Sep 18 07:46:47 PM UTC 24 Sep 18 07:46:50 PM UTC 24 53851976 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2658448915 Sep 18 07:46:43 PM UTC 24 Sep 18 07:46:50 PM UTC 24 682865496 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.2058955080 Sep 18 07:46:47 PM UTC 24 Sep 18 07:46:52 PM UTC 24 752843628 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.2298847606 Sep 18 07:46:51 PM UTC 24 Sep 18 07:46:53 PM UTC 24 87455021 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.3628811577 Sep 18 07:46:51 PM UTC 24 Sep 18 07:46:53 PM UTC 24 61148243 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.2662747776 Sep 18 07:46:51 PM UTC 24 Sep 18 07:46:53 PM UTC 24 43419886 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.678690517 Sep 18 07:46:51 PM UTC 24 Sep 18 07:46:54 PM UTC 24 53166546 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.506061054 Sep 18 07:46:51 PM UTC 24 Sep 18 07:46:54 PM UTC 24 150831468 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.149296307 Sep 18 07:46:51 PM UTC 24 Sep 18 07:46:54 PM UTC 24 192192958 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.1699592186 Sep 18 07:46:51 PM UTC 24 Sep 18 07:46:55 PM UTC 24 812517242 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2209297188 Sep 18 07:46:53 PM UTC 24 Sep 18 07:46:55 PM UTC 24 30313769 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.1103765697 Sep 18 07:46:53 PM UTC 24 Sep 18 07:46:55 PM UTC 24 86693187 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.2898019104 Sep 18 07:46:51 PM UTC 24 Sep 18 07:46:56 PM UTC 24 835769859 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.2797964773 Sep 18 07:46:54 PM UTC 24 Sep 18 07:46:56 PM UTC 24 40997135 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.1729000168 Sep 18 07:46:54 PM UTC 24 Sep 18 07:46:57 PM UTC 24 85294198 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.266423214 Sep 18 07:46:54 PM UTC 24 Sep 18 07:46:57 PM UTC 24 45842980 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.1837518428 Sep 18 07:46:54 PM UTC 24 Sep 18 07:46:57 PM UTC 24 843690613 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.3045845884 Sep 18 07:46:55 PM UTC 24 Sep 18 07:46:57 PM UTC 24 105877048 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.1100176432 Sep 18 07:46:54 PM UTC 24 Sep 18 07:46:57 PM UTC 24 225051127 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.1595052147 Sep 18 07:46:56 PM UTC 24 Sep 18 07:46:58 PM UTC 24 72963478 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.769579716 Sep 18 07:46:52 PM UTC 24 Sep 18 07:46:58 PM UTC 24 915734351 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2820860859 Sep 18 07:46:52 PM UTC 24 Sep 18 07:47:00 PM UTC 24 858079082 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.572038438 Sep 18 07:46:57 PM UTC 24 Sep 18 07:47:00 PM UTC 24 55876238 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.3748671609 Sep 18 07:46:56 PM UTC 24 Sep 18 07:47:00 PM UTC 24 709242243 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.2134503721 Sep 18 07:46:43 PM UTC 24 Sep 18 07:47:00 PM UTC 24 4182673592 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.131139732 Sep 18 07:47:00 PM UTC 24 Sep 18 07:47:02 PM UTC 24 38122443 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.1458002568 Sep 18 07:47:00 PM UTC 24 Sep 18 07:47:02 PM UTC 24 171121348 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.4244003919 Sep 18 07:47:00 PM UTC 24 Sep 18 07:47:02 PM UTC 24 104656142 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.746863773 Sep 18 07:47:00 PM UTC 24 Sep 18 07:47:03 PM UTC 24 178186846 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.3177869191 Sep 18 07:47:19 PM UTC 24 Sep 18 07:47:27 PM UTC 24 3354576448 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.2839874131 Sep 18 07:47:25 PM UTC 24 Sep 18 07:47:27 PM UTC 24 53035784 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.869522633 Sep 18 07:47:00 PM UTC 24 Sep 18 07:47:04 PM UTC 24 282401801 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.116785368 Sep 18 07:47:00 PM UTC 24 Sep 18 07:47:04 PM UTC 24 933136001 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.1628950473 Sep 18 07:47:02 PM UTC 24 Sep 18 07:47:04 PM UTC 24 56139877 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.2787576398 Sep 18 07:47:02 PM UTC 24 Sep 18 07:47:04 PM UTC 24 103247515 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.3140339968 Sep 18 07:47:02 PM UTC 24 Sep 18 07:47:04 PM UTC 24 48382930 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.4034605916 Sep 18 07:47:02 PM UTC 24 Sep 18 07:47:04 PM UTC 24 59040032 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.389181850 Sep 18 07:47:02 PM UTC 24 Sep 18 07:47:04 PM UTC 24 116101010 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.814052975 Sep 18 07:47:03 PM UTC 24 Sep 18 07:47:05 PM UTC 24 41821348 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.1853159212 Sep 18 07:47:03 PM UTC 24 Sep 18 07:47:05 PM UTC 24 94663578 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.4149580756 Sep 18 07:47:03 PM UTC 24 Sep 18 07:47:06 PM UTC 24 624624808 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.1671965172 Sep 18 07:47:05 PM UTC 24 Sep 18 07:47:07 PM UTC 24 50738881 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.2079082764 Sep 18 07:46:57 PM UTC 24 Sep 18 07:47:07 PM UTC 24 3496221760 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.1492043392 Sep 18 07:47:05 PM UTC 24 Sep 18 07:47:07 PM UTC 24 113474940 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.277387986 Sep 18 07:47:05 PM UTC 24 Sep 18 07:47:07 PM UTC 24 164579845 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.2013352895 Sep 18 07:47:05 PM UTC 24 Sep 18 07:47:07 PM UTC 24 458853010 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.2050843923 Sep 18 07:47:05 PM UTC 24 Sep 18 07:47:07 PM UTC 24 77843878 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1642187368 Sep 18 07:47:00 PM UTC 24 Sep 18 07:47:08 PM UTC 24 887304721 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.2345958489 Sep 18 07:47:06 PM UTC 24 Sep 18 07:47:08 PM UTC 24 125486279 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.1115965847 Sep 18 07:47:05 PM UTC 24 Sep 18 07:47:11 PM UTC 24 1956884172 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.385090472 Sep 18 07:47:06 PM UTC 24 Sep 18 07:47:12 PM UTC 24 896221525 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.164274926 Sep 18 07:47:06 PM UTC 24 Sep 18 07:47:12 PM UTC 24 858972624 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.3160385170 Sep 18 07:47:12 PM UTC 24 Sep 18 07:47:14 PM UTC 24 33284433 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.1351852250 Sep 18 07:47:03 PM UTC 24 Sep 18 07:47:14 PM UTC 24 3761578547 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.1741635517 Sep 18 07:47:12 PM UTC 24 Sep 18 07:47:14 PM UTC 24 47124311 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.1489911555 Sep 18 07:47:12 PM UTC 24 Sep 18 07:47:14 PM UTC 24 37008779 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.3755318753 Sep 18 07:47:25 PM UTC 24 Sep 18 07:47:27 PM UTC 24 46504276 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.559154204 Sep 18 07:47:13 PM UTC 24 Sep 18 07:47:14 PM UTC 24 121450208 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.1723805259 Sep 18 07:47:12 PM UTC 24 Sep 18 07:47:15 PM UTC 24 64364163 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.2371249420 Sep 18 07:47:12 PM UTC 24 Sep 18 07:47:15 PM UTC 24 85595234 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.3395099159 Sep 18 07:47:12 PM UTC 24 Sep 18 07:47:15 PM UTC 24 352157312 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.1639980079 Sep 18 07:47:13 PM UTC 24 Sep 18 07:47:15 PM UTC 24 54415551 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.97902271 Sep 18 07:47:12 PM UTC 24 Sep 18 07:47:15 PM UTC 24 343408895 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.2085703678 Sep 18 07:47:13 PM UTC 24 Sep 18 07:47:15 PM UTC 24 118027260 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.1510434361 Sep 18 07:47:14 PM UTC 24 Sep 18 07:47:16 PM UTC 24 221681702 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.1733318140 Sep 18 07:47:14 PM UTC 24 Sep 18 07:47:16 PM UTC 24 35584613 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.183723684 Sep 18 07:47:13 PM UTC 24 Sep 18 07:47:17 PM UTC 24 708946221 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.459982960 Sep 18 07:47:18 PM UTC 24 Sep 18 07:47:20 PM UTC 24 93433772 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1907259017 Sep 18 07:47:18 PM UTC 24 Sep 18 07:47:20 PM UTC 24 38207939 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.4190488453 Sep 18 07:47:18 PM UTC 24 Sep 18 07:47:20 PM UTC 24 38627639 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.2891670357 Sep 18 07:47:18 PM UTC 24 Sep 18 07:47:20 PM UTC 24 387200504 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.4293473416 Sep 18 07:47:18 PM UTC 24 Sep 18 07:47:20 PM UTC 24 59432402 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.3657117707 Sep 18 07:47:18 PM UTC 24 Sep 18 07:47:20 PM UTC 24 222537134 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.4047183304 Sep 18 07:47:19 PM UTC 24 Sep 18 07:47:21 PM UTC 24 69211641 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.769442548 Sep 18 07:47:18 PM UTC 24 Sep 18 07:47:21 PM UTC 24 153269341 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.343672473 Sep 18 07:47:18 PM UTC 24 Sep 18 07:47:21 PM UTC 24 44326367 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.3709590550 Sep 18 07:47:18 PM UTC 24 Sep 18 07:47:21 PM UTC 24 379679204 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.113417286 Sep 18 07:47:19 PM UTC 24 Sep 18 07:47:21 PM UTC 24 187466578 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.1758863315 Sep 18 07:47:18 PM UTC 24 Sep 18 07:47:21 PM UTC 24 52135033 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.3888379246 Sep 18 07:46:56 PM UTC 24 Sep 18 07:47:22 PM UTC 24 9548823207 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.560280498 Sep 18 07:47:18 PM UTC 24 Sep 18 07:47:23 PM UTC 24 779904788 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.1648853204 Sep 18 07:47:21 PM UTC 24 Sep 18 07:47:23 PM UTC 24 55800837 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2645912374 Sep 18 07:47:18 PM UTC 24 Sep 18 07:47:24 PM UTC 24 846519506 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.3698339078 Sep 18 07:47:22 PM UTC 24 Sep 18 07:47:24 PM UTC 24 19788331 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.3096698496 Sep 18 07:47:21 PM UTC 24 Sep 18 07:47:24 PM UTC 24 97830859 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.5834804 Sep 18 07:47:22 PM UTC 24 Sep 18 07:47:24 PM UTC 24 68731794 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1862791309 Sep 18 07:47:22 PM UTC 24 Sep 18 07:47:24 PM UTC 24 265323601 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3257212511 Sep 18 07:47:22 PM UTC 24 Sep 18 07:47:24 PM UTC 24 96277284 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.2512435641 Sep 18 07:47:21 PM UTC 24 Sep 18 07:47:24 PM UTC 24 430755316 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.3260027043 Sep 18 07:47:22 PM UTC 24 Sep 18 07:47:25 PM UTC 24 295882677 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.3932402966 Sep 18 07:47:23 PM UTC 24 Sep 18 07:47:25 PM UTC 24 28766921 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.2706154758 Sep 18 07:47:23 PM UTC 24 Sep 18 07:47:25 PM UTC 24 29380963 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.1767524781 Sep 18 07:47:23 PM UTC 24 Sep 18 07:47:26 PM UTC 24 109904778 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.491385854 Sep 18 07:47:23 PM UTC 24 Sep 18 07:47:26 PM UTC 24 204564633 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3904451764 Sep 18 07:47:22 PM UTC 24 Sep 18 07:47:26 PM UTC 24 808219039 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.2591298440 Sep 18 07:47:25 PM UTC 24 Sep 18 07:47:27 PM UTC 24 55738350 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.952207105 Sep 18 07:47:25 PM UTC 24 Sep 18 07:47:27 PM UTC 24 76746220 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.2641570064 Sep 18 07:47:25 PM UTC 24 Sep 18 07:47:27 PM UTC 24 57281069 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.262648941 Sep 18 07:47:25 PM UTC 24 Sep 18 07:47:28 PM UTC 24 115203167 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3992237420 Sep 18 07:47:22 PM UTC 24 Sep 18 07:47:28 PM UTC 24 878399800 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.3683087308 Sep 18 07:47:28 PM UTC 24 Sep 18 07:47:30 PM UTC 24 31205193 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.22837029 Sep 18 07:47:27 PM UTC 24 Sep 18 07:47:30 PM UTC 24 220368760 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.846565967 Sep 18 07:47:28 PM UTC 24 Sep 18 07:47:30 PM UTC 24 31401707 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2981802527 Sep 18 07:47:28 PM UTC 24 Sep 18 07:47:30 PM UTC 24 173682930 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.2644016709 Sep 18 07:47:25 PM UTC 24 Sep 18 07:47:30 PM UTC 24 2152900309 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.1924687748 Sep 18 07:47:27 PM UTC 24 Sep 18 07:47:30 PM UTC 24 239528675 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.287748771 Sep 18 07:47:27 PM UTC 24 Sep 18 07:47:30 PM UTC 24 258092170 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.2702223436 Sep 18 07:47:29 PM UTC 24 Sep 18 07:47:31 PM UTC 24 44881472 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.3636647042 Sep 18 07:47:29 PM UTC 24 Sep 18 07:47:31 PM UTC 24 52328249 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.3499531835 Sep 18 07:47:29 PM UTC 24 Sep 18 07:47:31 PM UTC 24 75083867 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.3912441505 Sep 18 07:47:29 PM UTC 24 Sep 18 07:47:32 PM UTC 24 376864462 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.3205002132 Sep 18 07:47:30 PM UTC 24 Sep 18 07:47:32 PM UTC 24 63782972 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.3808822054 Sep 18 07:47:29 PM UTC 24 Sep 18 07:47:32 PM UTC 24 154244438 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.4153740716 Sep 18 07:47:29 PM UTC 24 Sep 18 07:47:32 PM UTC 24 453435588 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.508396298 Sep 18 07:47:28 PM UTC 24 Sep 18 07:47:32 PM UTC 24 778009942 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3705915023 Sep 18 07:47:28 PM UTC 24 Sep 18 07:47:32 PM UTC 24 958195901 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2705623616 Sep 18 07:47:31 PM UTC 24 Sep 18 07:47:33 PM UTC 24 20461751 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.4051370806 Sep 18 07:47:31 PM UTC 24 Sep 18 07:47:33 PM UTC 24 59803255 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.717691625 Sep 18 07:47:31 PM UTC 24 Sep 18 07:47:33 PM UTC 24 160997058 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.1980645202 Sep 18 07:47:13 PM UTC 24 Sep 18 07:47:33 PM UTC 24 5216751914 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.88303022 Sep 18 07:47:31 PM UTC 24 Sep 18 07:47:33 PM UTC 24 236305530 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.4138970511 Sep 18 07:47:32 PM UTC 24 Sep 18 07:47:35 PM UTC 24 29090238 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.2599743025 Sep 18 07:47:33 PM UTC 24 Sep 18 07:47:35 PM UTC 24 57353173 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2340308371 Sep 18 07:47:32 PM UTC 24 Sep 18 07:47:35 PM UTC 24 130665258 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.2916003433 Sep 18 07:47:32 PM UTC 24 Sep 18 07:47:35 PM UTC 24 232952237 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.523409485 Sep 18 07:47:33 PM UTC 24 Sep 18 07:47:35 PM UTC 24 127675784 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.1401526745 Sep 18 07:47:32 PM UTC 24 Sep 18 07:47:35 PM UTC 24 34924150 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.1194148809 Sep 18 07:47:31 PM UTC 24 Sep 18 07:47:35 PM UTC 24 638102280 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.1569599775 Sep 18 07:47:34 PM UTC 24 Sep 18 07:47:36 PM UTC 24 217692826 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.3400437682 Sep 18 07:47:34 PM UTC 24 Sep 18 07:47:36 PM UTC 24 156429881 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.2453470512 Sep 18 07:47:34 PM UTC 24 Sep 18 07:47:36 PM UTC 24 44276582 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.2055562089 Sep 18 07:47:34 PM UTC 24 Sep 18 07:47:36 PM UTC 24 107776111 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.3315931418 Sep 18 07:47:34 PM UTC 24 Sep 18 07:47:37 PM UTC 24 113357471 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1095995956 Sep 18 07:47:32 PM UTC 24 Sep 18 07:47:37 PM UTC 24 1067356039 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.2316855842 Sep 18 07:47:31 PM UTC 24 Sep 18 07:47:38 PM UTC 24 3491666505 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.3711213847 Sep 18 07:47:36 PM UTC 24 Sep 18 07:47:38 PM UTC 24 38983537 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.3087427444 Sep 18 07:47:36 PM UTC 24 Sep 18 07:47:38 PM UTC 24 111224519 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.3255345073 Sep 18 07:47:36 PM UTC 24 Sep 18 07:47:38 PM UTC 24 75679705 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.733903016 Sep 18 07:47:36 PM UTC 24 Sep 18 07:47:38 PM UTC 24 24677471 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.2484927828 Sep 18 07:47:36 PM UTC 24 Sep 18 07:47:38 PM UTC 24 139167839 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.3722928955 Sep 18 07:47:36 PM UTC 24 Sep 18 07:47:38 PM UTC 24 41538846 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3125186026 Sep 18 07:47:32 PM UTC 24 Sep 18 07:47:39 PM UTC 24 791324432 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.2149418815 Sep 18 07:47:34 PM UTC 24 Sep 18 07:47:39 PM UTC 24 2227910320 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.829996 Sep 18 07:47:38 PM UTC 24 Sep 18 07:47:40 PM UTC 24 38266482 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.2045978220 Sep 18 07:47:38 PM UTC 24 Sep 18 07:47:40 PM UTC 24 59000079 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1304722721 Sep 18 07:47:38 PM UTC 24 Sep 18 07:47:40 PM UTC 24 90588113 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.3649616799 Sep 18 07:47:38 PM UTC 24 Sep 18 07:47:40 PM UTC 24 443781955 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.1836495887 Sep 18 07:47:40 PM UTC 24 Sep 18 07:47:41 PM UTC 24 74041565 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.3838561883 Sep 18 07:47:40 PM UTC 24 Sep 18 07:47:42 PM UTC 24 75366491 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.2354093443 Sep 18 07:47:40 PM UTC 24 Sep 18 07:47:42 PM UTC 24 67532296 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.3186696573 Sep 18 07:47:40 PM UTC 24 Sep 18 07:47:42 PM UTC 24 459993440 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.3214620071 Sep 18 07:47:40 PM UTC 24 Sep 18 07:47:42 PM UTC 24 53003949 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.3947052363 Sep 18 07:47:40 PM UTC 24 Sep 18 07:47:42 PM UTC 24 99328774 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3455230108 Sep 18 07:47:38 PM UTC 24 Sep 18 07:47:42 PM UTC 24 821147141 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.93705445 Sep 18 07:47:41 PM UTC 24 Sep 18 07:47:43 PM UTC 24 162873491 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.1134915707 Sep 18 07:47:42 PM UTC 24 Sep 18 07:47:43 PM UTC 24 24947634 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.817175372 Sep 18 07:47:41 PM UTC 24 Sep 18 07:47:44 PM UTC 24 168235147 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1585565071 Sep 18 07:47:38 PM UTC 24 Sep 18 07:47:44 PM UTC 24 797166019 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.2468152999 Sep 18 07:47:41 PM UTC 24 Sep 18 07:47:44 PM UTC 24 291656293 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.2096620369 Sep 18 07:47:42 PM UTC 24 Sep 18 07:47:44 PM UTC 24 400836206 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.4021630002 Sep 18 07:47:25 PM UTC 24 Sep 18 07:47:44 PM UTC 24 11257770279 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.975888287 Sep 18 07:47:43 PM UTC 24 Sep 18 07:47:45 PM UTC 24 31150723 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3951575432 Sep 18 07:47:42 PM UTC 24 Sep 18 07:47:45 PM UTC 24 1502749377 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.4004121992 Sep 18 07:47:43 PM UTC 24 Sep 18 07:47:45 PM UTC 24 97203169 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.647945799 Sep 18 07:47:43 PM UTC 24 Sep 18 07:47:45 PM UTC 24 32154772 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2232510883 Sep 18 07:47:43 PM UTC 24 Sep 18 07:47:45 PM UTC 24 56304394 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.3276118990 Sep 18 07:47:43 PM UTC 24 Sep 18 07:47:45 PM UTC 24 397524308 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.2600199862 Sep 18 07:47:43 PM UTC 24 Sep 18 07:47:45 PM UTC 24 302192945 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.3244889782 Sep 18 07:47:34 PM UTC 24 Sep 18 07:47:46 PM UTC 24 2846832047 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2489797013 Sep 18 07:47:43 PM UTC 24 Sep 18 07:47:47 PM UTC 24 1933983118 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.2145074191 Sep 18 07:47:40 PM UTC 24 Sep 18 07:47:47 PM UTC 24 2142915521 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.4178005839 Sep 18 07:47:45 PM UTC 24 Sep 18 07:47:47 PM UTC 24 53329226 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.282052600 Sep 18 07:47:45 PM UTC 24 Sep 18 07:47:47 PM UTC 24 60926526 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.3485604654 Sep 18 07:47:45 PM UTC 24 Sep 18 07:47:47 PM UTC 24 80573056 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.3803545488 Sep 18 07:47:45 PM UTC 24 Sep 18 07:47:47 PM UTC 24 181347097 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.253592817 Sep 18 07:47:45 PM UTC 24 Sep 18 07:47:48 PM UTC 24 899601249 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.3417363981 Sep 18 07:47:46 PM UTC 24 Sep 18 07:47:48 PM UTC 24 99045181 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.1679639976 Sep 18 07:47:46 PM UTC 24 Sep 18 07:47:48 PM UTC 24 34791108 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.2127925705 Sep 18 07:47:47 PM UTC 24 Sep 18 07:47:49 PM UTC 24 29636183 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.4034245409 Sep 18 07:47:47 PM UTC 24 Sep 18 07:47:49 PM UTC 24 47924341 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3173101182 Sep 18 07:47:47 PM UTC 24 Sep 18 07:47:49 PM UTC 24 176833813 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.848221269 Sep 18 07:47:46 PM UTC 24 Sep 18 07:47:49 PM UTC 24 83494073 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.851884652 Sep 18 07:47:46 PM UTC 24 Sep 18 07:47:49 PM UTC 24 255211929 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.1974199930 Sep 18 07:47:48 PM UTC 24 Sep 18 07:47:50 PM UTC 24 89596919 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.2601969027 Sep 18 07:47:48 PM UTC 24 Sep 18 07:47:51 PM UTC 24 59543834 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.936429317 Sep 18 07:47:48 PM UTC 24 Sep 18 07:47:51 PM UTC 24 1051936676 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.1172210422 Sep 18 07:47:49 PM UTC 24 Sep 18 07:47:51 PM UTC 24 60489122 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.682310522 Sep 18 07:47:49 PM UTC 24 Sep 18 07:47:51 PM UTC 24 162490340 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.434828395 Sep 18 07:47:47 PM UTC 24 Sep 18 07:47:51 PM UTC 24 1058225904 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.2726587011 Sep 18 07:47:48 PM UTC 24 Sep 18 07:47:51 PM UTC 24 58876093 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2140612986 Sep 18 07:47:47 PM UTC 24 Sep 18 07:47:51 PM UTC 24 789151789 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.2283429647 Sep 18 07:47:48 PM UTC 24 Sep 18 07:47:51 PM UTC 24 230076324 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.1284106577 Sep 18 07:47:50 PM UTC 24 Sep 18 07:47:52 PM UTC 24 80794183 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.2633571909 Sep 18 07:47:50 PM UTC 24 Sep 18 07:47:52 PM UTC 24 50290594 ps
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